Circuit simulation method for a circuit realized by an LSI layou

Details Circuit simulation method for a circuit realized by an LSI layou Circuit simulation method for a circuit realized by an LSI layou

1990-09-04

1995-05-16

Trans, Vincent N.

Boots, shoes, and leggings

364578, G06F 1560

Patent

active

054167175

ABSTRACT:
In verifying an LSI layout pattern, the whole layout pattern is converted into circuit data and a subcircuit to be verified is picked up and subjected to simulation. After converting the layout pattern into the transistor level circuit data, the transistor level circuit data is transformed into a logic gate level circuit data while judging a clocked gate included in the subcircuit. After picking up a subcircuit in a predetermined manner, an approximate load is connected to the interface port of the picked-up subcircuit.

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