Circuit providing load isolation and memory domain...

Details Circuit providing load isolation and memory domain... Circuit providing load isolation and memory domain...

2011-06-21

2011-06-21

Sofocleous, Alexander (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S051000, C365S149000, C365S230030, C365S233130

Reexamination Certificate

active

07965579

ABSTRACT:
A circuit is configured to be mounted on a memory module configured to be operationally coupled to a computer system. The memory module has a first number of ranks of double-data-rate (DDR) memory devices configured to be activated concurrently with one another in response to a first number of chip-select signals. The circuit is configurable to receive a set of signals comprising address signals and a second number of chip-select signals, the address signals comprising bank address signals. The circuit is further configurable to monitor command signals received by the memory module, to selectively isolate a load of at least one rank of the first number of ranks from the computer system in response to the command signals, and to provide the first number of chip-select signals to the first number of ranks in response at least in part to the received bank address signals and the received second number of chip-select signals.

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