Circuit providing a negative resistance to offset error...

Details Circuit providing a negative resistance to offset error... Circuit providing a negative resistance to offset error...

1999-09-17

2001-05-08

Mottola, Steven J. (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S257000

Reexamination Certificate

active

06229394

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to circuitry used to compensate for error currents generated by common base transistors due to the Early Effect. More particularly, this invention relates to such error compensation circuitry used with folded cascode amplifiers.
2. Description of the Related Art
FIG. 1
shows circuitry for a conventional folded cascode amplifier. As shown, the folded cascode amplifier includes a differential amplifier with first and second transistors
100
and
102
. The base of transistor
100
receives an inverting input (V
IN−
), while the base of transistor
102
receives a noninverting input (V
IN+
). A current source
104
connects a positive power supply rail voltage (V+) to the emitters of transistors
100
and
102
. The collector of transistor
100
is connected by a resistor
110
having a value R
1
to a negative power supply rail voltage (V−), while the collector of transistor
102
is connected by a resistor
112
having a value R
2
to the V− power supply rail.
The current developed by the differential amplifier is “folded” back to provide a current to comply with more positive signal swings at a gain node (G) using circuitry including third and fourth transistors
120
and
122
connected in a common base configuration. The gain node G is connected to the collector of transistor
122
and to the input of a buffer
126
, the output of the buffer
126
forming the output V
OUT
of the amplifier. Transistor
120
has an emitter connected to the collector of transistor
102
and a collector connected to the input of a current mirror
124
, while transistor
122
has an emitter connected to the collector of transistor
100
and a collector connected to the output of current mirror
124
. The bases of transistors
120
and
122
are connected together through a voltage bias circuit
128
to the V− power supply rail.
Under ideal conditions, resistors
110
and
112
can be replaced with electronic current sinks. With electronic current sinks, differential signal currents from the collector of transistors
100
and
102
will travel through transistors
120
and
122
largely unmodified, insensitive to differing parameters in transistors
120
and
122
. However, resistors
110
and
112
are typically used instead of the current sinks because the voltage swing at the inputs V
IN−
and V
IN+
will not be limited by a minimum operating voltage which an electronic current sink requires. When resistors
110
and
112
are utilized, the V− and V+ power supply rails may be designed to place as low as 150 mV across the resistors
110
and
112
. Further, either of the inputs V
IN+
or V
IN−
can go all the way to the V− rail voltage and the amplifier still work properly.
With resistors
110
and
112
used instead of electronic current sinks, a difference between the collector to emitter voltages (V
CE
S) of transistors
120
and
122
creates an offset voltage V
OS
across the inputs V
IN+
and V
IN−
, requiring an unbalanced input voltage to correct. For transistor
120
, almost the entire voltage potential difference between the V+ and V− rails is applied as its V
CE
, while only about half of the potential difference between the V+ and V− rails is applied as the V
CE
of transistor
122
. Such a difference in V
CE
S occurs because the collector of transistor
122
is coupled to a the input of buffer
126
which has a nominal voltage value of 0 volts. The imbalance in the V
CE
voltages between common base transistors
120
and
122
causes a corresponding imbalance in the base to emitter voltage (V
BE
) of transistors
120
and
122
due to the Early Effect. A difference in V
BE
voltages in transistors
120
and
122
places unbalanced voltages across resistors
110
and
112
, generating an offset voltage V
OS
at the inputs V
IN−
and V
IN+
. The offset V
OS
voltage can be represented as follows:
V
OS
=vtln((V+−V
OUT
)/V
A
)/R
N
g
m
where vt is 26 mV at room temperature, V
A
is the Early Voltage of one of the respective transistors
120
or
122
, g
m
is the transconductance of the respective transistor, and R
N
is the resistance of the resistor
110
or
112
connected to the respective transistor
120
or
122
. The offset voltage V
OS
can be as much as a 10 mV.
With the offset voltage V
OS
as represented above, an overall gain reduction occurs for the amplifier due to the offset voltage V
OS
varying with the output voltage V
OUT
. Further, thermal noise performance is degraded, being effectively amplified and referred from the emitters of transistors
120
and
122
to the inputs of the amplifier. With V
OS
further varying with the supply voltage, V+, attempts to trim V
OS
for particular transistor parameters will be thwarted.
U.S. Pat. No. 5,168,243 entitled “Integrated High Gain Amplifier” discloses circuitry for increasing gain in a folded cascode amplifier by limiting V
OS
. The circuitry includes a current source driving cross coupled transistors connected to compensate for imbalance between transistors
120
and
122
. The cross coupled transistors include a pair of transistors with a first transistor having a base coupled to the collector of a second transistor, and the second transistor having a base coupled to the collector of the first transistor. The current source feeds the emitters of the cross coupled transistors and is tuned to reduce any imbalance between transistors
120
and
122
.
SUMMARY OF THE INVENTION
The present invention provides an improved method for cancellation of the error offset voltage V
OS
in a folded cascode amplifier.
The present invention includes circuitry which does not require tuning to cancel error offset voltage V
OS
, as opposed to the circuitry described in U.S. Pat. No. 5,168,243.
The present invention further provides cancellation of the error offset voltage irrespective of temperature changes.
In accordance with the present invention, an error offset voltage cancellation circuit is provided including, referring to
FIG. 2
, resistors
210
and
212
, a current source
214
connected to a first end of resistors
210
and
212
, and cross coupled transistors
220
and
222
connecting second ends of resistors
210
and
212
to the emitters of transistors
120
and
122
. The resistors
210
and
212
have resistance values R
1
′ and R
2
′ matching the respective values R
1
and R
2
. As connected, the cross coupled transistors
220
and
222
and resistors
210
and
212
effectively form a negative resistance −(R
1
+R
2
) to cancel error voltage between the emitters of transistors
120
and
122
.
Because the resistors
210
and
212
have values R
1
′ and R
2
′ matching the values R
1
and R
2
of resistors
110
and
112
enabling cancellation of an offset voltage, no tuning is required. Further, with temperature changes, any changes in resistance values
110
and
112
will be matched by a similar change in the resistance value of resistors
210
and
212
. Retuning will, thus, not be required with changes in temperature.
In an additional embodiment, referring to
FIG. 3
, the present invention includes transistors
320
and
322
which connect the cross coupled transistors
220
and
222
to the resistors
110
and
112
. Transistors
320
and
322
serve to compensate for any output offset errors due to the added impedance of transistors
220
and
222
.
In addition to use with common base transistors
120
and
122
of a folded cascode amplifier, the negative resistance circuits shown in
FIGS. 2 and 3
can serve to eliminate offset error voltage in other circuits which include common base transistors driving two separate resistors, as illustrated in FIGS.
4
and
5
.


REFERENCES:
patent: 4600893 (1986-07-01), Sugimoto
patent: 5168243 (1992-12-01), Feliz et al.
Toumazou, C., et al.,Analogue IC design the current-mode approach,IEE Circuits and Systems Series 2, pp. 70-81,

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