Circuit property verification system

Data processing: structural design – modeling – simulation – and em – Simulating nonelectrical device or system – Mechanical

Reexamination Certificate

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Details

C703S014000, C703S015000, C703S017000, C716S030000

Reexamination Certificate

active

06985840

ABSTRACT:
Described herein is a system for verifying that a circuit described by a hardware description language file has a property of responding to an antecedent event represented by a particular pattern in its input signals by exhibiting a consequent behavior of producing a particular pattern in its output signals during a finite time following the antecedent event. The system includes a conventional circuit simulator for simulating the behavior of the circuit under conditions defined by a user-provided test bench. The simulator produces output waveform data representing the behavior of the circuit input, output and internal signals, including signals representing the circuit's state. When the output waveform data indicates the antecedent event has occurred, the system determines the current state of the circuit from the waveform data. The system then creates and analyzes a temporally expanded model of the circuit to verify whether, starting from that current state, the circuit will exhibit the consequent behavior within that finite time under all input signal conditions.

REFERENCES:
patent: 5263149 (1993-11-01), Winlow
patent: 5465216 (1995-11-01), Rotem et al.
patent: 5513122 (1996-04-01), Cheng et al.
patent: 5745501 (1998-04-01), Garner et al.
patent: 5859962 (1999-01-01), Tipon et al.
patent: 5901073 (1999-05-01), Kurshan et al.
patent: 5905883 (1999-05-01), Kasuya
patent: 5913022 (1999-06-01), Tinaztepe et al.
patent: 5937183 (1999-08-01), Ashar et al.
patent: 5966516 (1999-10-01), De Palma et al.
patent: 5974575 (1999-10-01), Fujimoto
patent: 6009531 (1999-12-01), Selvidge et al.
patent: 6115763 (2000-09-01), Douskey et al.
patent: 6138266 (2000-10-01), Ganesan et al.
patent: 6311293 (2001-10-01), Kurshan et al.
patent: 6321186 (2001-11-01), Yuan et al.
patent: 6339837 (2002-01-01), Li
patent: 6449752 (2002-09-01), Baumgartner et al.
patent: 6484134 (2002-11-01), Hoskote
patent: 6496953 (2002-12-01), Helland
Rabiei det al., “Model order reduction of large circuits using balanced truncation”, IEEE 1999.
Schlipf et al., “An easy approach to formal verification”, IEEE 1997.

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