Circuit partitioning technique for use with multiplexed inter-co

Details Circuit partitioning technique for use with multiplexed inter-co Circuit partitioning technique for use with multiplexed inter-co

1996-01-19

1998-12-29

Voeltz, Emanuel Todd

Boots, shoes, and leggings

364490, 364491, 364578, G06F 1750, G06F 9455

Patent

active

058547525

ABSTRACT:
A method for partitioning a logic circuit is provided for emulation under a virtual wires method using programmable logic devices. Because a virtual wires systems replace pin constraints by a corresponding gate constraint, partitioning for a virtual wires system applies novel constraints and algorithms. In one embodiment, partitioning is provided under a "flat mincut" approach in conjunction with a virtual wire cost constraint. In another embodiment, partitioning is provided under a "hierarchical mincut" in conjunction with a virtual wire cost constraint.

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