Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-05-30
2004-09-07
Liang, Regina (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S204000
Reexamination Certificate
active
06788281
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-163788, filed May 31, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a flat-panel display device in which signal wirings are formed along pixel electrodes arranged in a matrix form and, more particularly to an output circuit connected to an end of the signal wiring to drive the signal wiring, serving as a capacitive load in the flat-panel display device.
In recent years, active matrix type liquid crystal display devices have become popular as monitor displays of notebook-size personal computers and portable terminal devices because of the fine and clear images they can display and the high reliability of the products. Such a liquid crystal display device generally comprises an array substrate having a matrix array of pixel electrodes, a counter substrate having a counter electrode arranged to face the pixel electrodes, and a liquid crystal layer held between the array substrate and the counter substrate. The array substrate includes a plurality of scanning lines arranged along the rows of the pixel electrodes, a plurality of signal lines arranged along the columns of the pixel electrodes and a plurality of switching elements arranged near the intersections of the scanning lines and the signal lines in addition to the plurality of pixel electrodes. Each of the switching elements is connected to apply the signal voltage of a corresponding signal line to a corresponding pixel electrode when the switching element is driven via a corresponding scanning line. The use of the switching elements provides a high contrast image while sufficiently reducing crosstalk between adjacent pixels.
A switching element is generally formed of a thin film transistor using a semiconductor thin film of amorphous silicon. Recent progress of production technology has enabled a semiconductor thin film of polysilicon, whose mobility is higher than that of amorphous silicon, to be formed on a glass plate at low temperatures. With thin film production technology, a scanning line driver and a signal line driver may be formed together with the switching elements for pixels on the array substrate.
The demand for liquid crystal display devices with a larger screen size is currently increasing. If the liquid crystal display device has a conventional screen size of about 12 inches, signal wirings such as the scanning lines or the signal lines may be sufficiently driven by means of a single driver. The capacitive load of the signal wirings increases upon an increase in the screen size. Therefore, there is a case where the driving ability of the driver becomes insufficient due to an increase in the capacitive load. Recently, there is a trend of employing a dual-side driving system where a pair of drivers are connected to the respective ends of signal wirings in order to solve this problem. However, the existing thin film production technology is unable to uniformly form polysilicon films having excellent properties on a glass plate. Therefore, the output characteristics of the drivers are likely to be uneven on the glass plate.
Conventionally, the scanning line driver includes an output circuit provided for each scanning line and has the structure shown in FIG.
5
. In the output circuit, a NOR circuit
1
selectively outputs a scanning signal SEL under the control of an output control signal SHUT. The scanning signal SEL output from the NOR circuit
1
is level-shifted by a level shifter LS and then supplied to a scanning line Y
1
via inverters
2
and
3
.
The level shifter LS shifts the level of the input signal the level of which may vary between respective higher and lower power source potentials YVDD and YVSS to produce an output signal the level of which may vary between respective higher and lower power source potentials YGVDD and YGVSS. The level shifter LS drives the load connected to its output terminal by a series circuit of two N-channel transistors, or, a single P-channel transistor. Since the series circuit of two N-channel transistors and the P-channel transistor have the same driving ability. It is unknown whether the output terminal is set at the higher power source potential YGVDD or the lower power source potential YGVSS immediately after supply of power. If two scanning line drivers of the aforementioned configuration may be connected to the ends of the scanning line Y
1
, respectively. Further, these drivers, which differ in characteristics, may set the power source potential YGVDD to one end of the scanning line Y
1
and the lower power source potential YGVSS to the other end of the scanning line Y
1
immediately after supply of power. In this case, a short-circuit current flows through both scanning line drivers and through the scanning line Y
1
. Consequently, the power source may be shut down or broken down, disabling the liquid crystal display device from operation normally.
This problem can be avoided by a protection circuit added to the inverter
3
and having a P-channel transistor
3
A and an N-channel transistor
3
B shown in FIG.
6
. The inverter
3
has a P-channel transistor
3
C connected in series with the P-channel transistor
3
A between power source terminal YGVDD and the scanning line Y
1
, and an N-channel transistor
3
D connected in series with the N-channel transistor
3
B between the scanning line Y
1
and power source terminal YGVSS. In this case, the level shifter LS receives the scanning signal SEL supplied without passing through the NOR circuit
1
to supply an output signal to both the gate electrodes of the P- and N-channel transistors
3
C and
3
D. The output control signal SHUT is supplied directly to the gate electrode of the N-channel transistor
3
B and indirectly to the gate electrode of the P-channel transistor
3
A via an inverter INV. With the above-described arrangement, the transistors
3
A and
3
B of the protection circuit are maintained nonconductive for a while upon supply of power under the control of the output control signal SHUT so that the scanning line Y
1
can be set into an electrically-floating state to prevent a short-circuit current from flowing therethrough. However, the transistors
3
A and
3
B are required to be as large as the transistors
3
C and
3
D of the final inverter
3
that are the largest circuit elements in the scanning line driver. Therefore, it is extremely difficult to determine their layout without increasing the width of the frame that surrounds the display area in the liquid crystal display device.
BRIEF SUMMARY OF THE INVENTION
In view of the aforementioned problems, an object of the present invention is to provide a circuit panel and a flat-panel display device that can reduce the difficulty in layout while suppressing undesirable charges from being supplied to the signal wiring immediately after supply of power.
Another object of the present invention is to provide a circuit panel and a flat-panel display device that can effectively prevent any short-circuit current from flowing through the signal wiring immediately after supply of power.
In an aspect of the present invention, there is provided a circuit panel which comprises a signal wiring formed on an insulating substrate and an output circuit disposed at an end of the signal wiring, for supplying one of first and second voltages to the signal wiring according to an external voltage and a timing signal, wherein the output circuit includes a plurality of circuit elements whose driving abilities are uneven, to output the first voltage upon receipt of the external voltage.
In another aspect of the invention, there is provided a flat-panel display device which comprises first and second substrates and an optical modulation layer held between the substrates, wherein the first substrate includes first signal wirings, second signal wirings almost perpendicularly intersecting the first signal wirings, pixel transistors disposed ne
Ando Kotaro
Aoki Yoshiro
Kabushiki Kaisha Toshiba
Liang Regina
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