Circuit package and method of plating the same

Details Circuit package and method of plating the same Circuit package and method of plating the same

2006-03-28

2006-03-28

Smith, Matthew (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S706000, C257S712000

Reexamination Certificate

active

07019394

ABSTRACT:
A circuit package includes a base portion and a first metal pattern disposed on a substrate surface. Second and third metal patterns are disposed on another substrate surface, and electrically coupled to first and second vias. The third metal pattern forms a gap to electrically isolate it from the second metal pattern. A circuit package includes a substrate having an opening and a single heat sink positioned in the opening to expose top and bottom surfaces through top and bottom surfaces of the substrate. Selective plating includes applying first and second metal patterns to a substrate surface, creating a potential voltage difference between the first metal pattern and a metal source, and plating the first metal pattern by attracting a first metal type to the voltage potential of the first metal pattern. The voltage potential of the first metal pattern is less than the voltage potential of the metal source.

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“Thermal VIA/BGA”, Micro Substrates Corporation, website, 3 pages, © 2000, found at: http://www.microsubstrates.com/body—thermal%20via—bga.html. on Sep. 13, 2003.
Technical Schematic entitled “Modification of Ceramic Detail, Thickness & Base,” dated Jan. 29, 2003, Kyocera Corporation.

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