Circuit output stage protection system

Details Circuit output stage protection system Circuit output stage protection system

2007-06-19

2007-06-19

Jackson, Stephen W (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific voltage responsive fault sensor

Reexamination Certificate

active

10751508

ABSTRACT:
An output stage protection system for protecting NMOS devices in an integrated circuit (IC) output stage during normal operations and power up/power down. In an embodiment, the output stage includes a pair of relatively low voltage NMOS devices coupled to a current source and IC core outputs. A first pair of relatively high voltage NMOS devices is coupled to the relatively low voltage pair and a biasing circuit. A second pair of relatively high voltage NMOS devices is coupled to a resistor, the first pair, and first and second output nodes, respectively. One or more diodes are coupled in series between the first and second output nodes and the resistor. In an embodiment, the output stage protection system protects NMOS devices in the output stage from electrostatic discharge (ESD). Input/output (I/O) pad ESD protection circuits are coupled to the I/O pads and include a clamp coupled to a local net.

REFERENCES:
patent: 5420527 (1995-05-01), Naber
patent: 5821799 (1998-10-01), Saripella
patent: 6384685 (2002-05-01), Juang
patent: 6891433 (2005-05-01), Schrader

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