Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Reexamination Certificate
2007-03-06
2007-03-06
Nguyen, Tuan T. (Department: 2824)
Static information storage and retrieval
Addressing
Including particular address buffer or latch circuit...
C365S233100
Reexamination Certificate
active
10904267
ABSTRACT:
A data communication circuit of a SDRAM for data communication comprises a plurality of data lines coupled to a plurality of data pins. The number of the data lines, according to an embodiment of the present invention, is less than the number of the data pins. When the data communication circuit receives/outputs data, one of the LDQM pin and the UDQM pin are enabled to receive/output a first part of the data. The other LDQM pin and the UDQM pin are enabled. Accordingly, the data communication circuit of the SDRAM, according to an embodiment of the present invention, is capable of transmitting more data using a bus with a narrow width.
REFERENCES:
patent: 6496403 (2002-12-01), Noda et al.
patent: 6867993 (2005-03-01), Ohshima et al.
patent: 6944092 (2005-09-01), Kang
Chen Yuan-Ning
Liao Jen-Yi
Liu Chao-Yung
Yang Ying-Chih
Jiang Chyun IP Office
Nguyen Tuan T.
Sunplus Technology Co. Ltd.
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