Circuit module

Details Circuit module Circuit module

1998-08-10

2002-05-21

Picard, Leo P. (Department: 2841)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S760000, C361S772000, C361S783000, C361S764000, C257S686000, C257S777000, C439S059000, C439S061000, C439S062000, C228S180210, C228S180100

Reexamination Certificate

active

06392897

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit module including semiconductor ICs mounted on a printed wiring board and, more particularly, to a memory module which achieves an increased signal transfer rate.
2. Description of the Background Art
A circuit module comprises a plurality of semiconductor ICs having the same function and mounted on a printed wiring board in conjunction with a control IC, as required. The most common semiconductor ICs to be mounted include a memory IC. Thus, description will now be given using a memory module as an example.
FIG. 16
is a front view of a conventional memory module
101
. A plurality, illustrated herein as four, of memory ICs
103
are mounted on a printed wiring board
102
. Each of the memory ICs
103
includes pins DQ
0
to DQ
n
which are data pins for inputting and outputting data signals where n is a natural number. For example, n=7 when a memory IC
103
has eight data pins. The reference character DQ
t
(0≦t≦n) is used hereinafter to generically represent the data pins. An individual data signal is inputted to and outputted from each data pin DQ
t
of each of the memory ICs
103
. Thus, when the four memory ICs
103
each having eight data pins are mounted on the printed wiring board
102
as shown in
FIG. 16
, 32 (4×8) connector terminals among a plurality of connector terminals
104
of the memory module
101
function as connector terminals
104
a
for the data signals. The connector terminals
104
a
and the data pins DQ
0
to DQ
n
are connected to each other by interconnect lines
105
a
provided on the printed wiring board
102
. For purposes of simplification, only the connection between the data pins DQ
0
to DQ
n
of one of the memory ICs
103
which is positioned at the top of the drawing paper (or the rightmost memory IC
103
) and the connector terminals
104
is typically shown in FIG.
16
.
Each of the memory ICs
103
further includes pins A
0
to A
k
which are address/command pins for inputting address signals or command signals (referred to hereinafter together as “address/command signals”) to each memory IC
103
where k is a natural number. For example, k=7 when a memory IC
103
has eight address/command pins. The reference character A
s
(0≦s≦k) is used hereinafter to generically represent the address/command pins. Unlike the data signals to be inputted and outputted, an address/command signal is commonly inputted to the address/command pins A
s
of the respective memory ICs
103
. Thus, when each of the memory ICs
103
includes eight address/command pins as shown in
FIG. 16
, eight connector terminals among the plurality of connector terminals
104
of the memory module
101
function as connector terminals
104
b
for the address/command signals. An interconnect line
105
b
provided on the printed wiring board
102
is connected to each of the plurality of connector terminals
104
b.
FIG. 17
is a sectional view of the memory module
101
, and particularly shows the memory module
101
in section as viewed in the direction of the arrow Y
1
of FIG.
16
. With reference to
FIGS. 16 and 17
, the connection between the interconnect line
105
b
and the address/command pins A
s
is described hereinafter. Since the interconnect lines
105
a
are provided on the printed wiring board
102
as described above, an interconnect line for connecting the interconnect line
105
b
and the address/command pins A
s
is not permitted to be provided on the printed wiring board
102
. For this reason, a lower interconnect line
105
c
extending in the direction perpendicular to the longitudinal direction of the interconnect line
105
b
is provided inside the printed wiring board
102
, and the interconnect line
105
b
and the lower interconnect line
105
c
are connected to each other by a conductor which fills a through hole
106
. Interconnect lines
108
for connection to the address/command pins A
s
are provided on the printed wiring board
102
, and the interconnect lines
108
and the lower interconnect line
105
c
are connected to each other by a conductor which fills through holes
107
. In this manner, the connection is established between the interconnect line
105
b
and the address/command pins A
s
. This allows an address/command signal applied to the connector terminal
104
b
from the exterior to be transmitted in sequential order through the interconnect line
105
b
, the conductor which fills the through hole
106
, the lower interconnect line
105
c
, the conductor which fills the through holes
107
, the interconnect lines
108
, and the address/command pins A
s
to the memory ICs
103
.
FIG. 18
is a side view of the general configuration of a system including a plurality of memory modules each corresponding to the memory module
101
. A signal line
111
is provided on a motherboard
109
. The signal line
111
is connected at one end thereof to a controller
110
disposed on the motherboard
109
, and is connected at the other end thereof to a terminating resistor
112
provided on the motherboard
109
. The terminating resistor
112
is connected to a power supply
113
for providing a termination potential. A plurality of connectors
114
arranged at regularly spaced intervals in the longitudinal direction of the signal line
111
are provided also on the motherboard
109
. The connectors
114
function to physically support the memory modules
101
inserted therein. The insertion of the plurality of memory modules
101
in the respective connectors
114
causes each of the plurality of memory modules
101
to be placed in an upright position, or to extend in the direction perpendicular to the longitudinal direction of the signal line
111
. It should be noted that a connector
114
in which no memory module
101
is inserted as shown in
FIG. 18
is present in some cases. The connectors
114
also function to establish electrical connection between the connector terminals
104
(not shown in
FIG. 18
) of the memory modules
101
and the signal line
111
. Thus, the data signals and address/command signals outputted from the controller
110
are transmitted through the signal line
111
and the connectors
114
to the memory modules
101
. The symbol d shown in
FIG. 18
denotes the spacing (pitch) between adjacent memory modules
101
.
FIG. 19
is a sectional view of the connector
114
with the memory module
101
inserted therein, and particularly shows the memory module
101
in section as viewed in the direction of the arrow Y
2
of FIG.
16
. The interconnect line
105
a
and the data pins DQ
t
are illustrated in
FIG. 19. A
connector pin
115
b
and a conductive connector pin
115
a
which are on opposite sides of the memory module
101
hold the memory module
101
therebetween, thereby to support the memory module
101
in the connector
114
. Electrical connection between the signal line
111
and the connector terminal
104
a
is made through the connector pin
115
a.
With the increase in processor operating speeds, there has been a need to increase the signal transfer rate of the memory modules. Unfortunately, the conventional memory modules
101
described above present drawbacks to be described below in terms of the increase in the signal transfer rate, and are not capable of responding the need.
One of the drawbacks is as follows. The data signals must be synchronized when inputted to and outputted from the data pins DQ
0
to DQ
n
of the memory IC
103
. In the memory module
101
shown in
FIG. 16
, however, there is a significant difference in length between an interconnect line
105
a
0
connected to the data pin DQ
0
and an interconnect line
105
a
n
connected to the data pin DQ
n
, for example. If the data signals inputted from the controller
110
to the memory IC
103
are synchronous with each other on the signal line
111
, the difference in length between the interconnect lines
105
a
causes the synchronism to be lost, resulting in phase differences between the data signals

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