Circuit, method and/or architecture for improving the...

Details Circuit, method and/or architecture for improving the... Circuit, method and/or architecture for improving the...

1999-08-09

2003-09-23

Ton, Dang (Department: 2666)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C370S230000, C370S458000, C370S508000, C375S327000, C375S376000

Reexamination Certificate

active

06625177

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to communication devices generally and, more particularly, to a circuit, method and/or architecture for improving the performance of a serial communication link.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a block diagram illustrating a communications circuit
10
is shown. The circuit
10
comprises a number of ports
14
a
-
14
n
. Each of the ports
14
a
-
14
n
comprises receive block
16
, a transmit block
18
and a multiplexer
20
.
The ports
14
a
-
14
n
are connected to each other via serial links
21
a
-
21
n
and
22
a
-
22
n
. The ports
14
a
-
14
n
each comprise serial inputs
24
a
-
24
n
,
26
a
-
26
n
and
28
a
-
28
n
, and serial outputs
25
a
14
25
n
,
27
a
-
27
n
and
29
a
-
29
n
, respectively. The serial connection from each port
14
a
-
14
n
to another port
14
a
-
14
n
is in both directions (i.e., both receive and transmit communication). The data arrives in the transmit block
18
a
-
18
n
from a parallel interface
15
a
-
15
n
, respectively, for each port
14
a
-
14
n
. The data is then transmitted through a selectable multiplexer
20
a
-
20
n
to the serial outputs
25
a
-
25
n
,
27
a
-
27
n
and/or
29
a
-
29
n
. The serial outputs
25
a
-
25
n
,
27
a
-
27
n
and/or
29
a
-
29
n
transmit the data to one of the serial communication links
22
a
-
22
n.
For the receive side, the data is received from one of the serial communication links
21
a
-
21
n
or
22
a
-
22
n
at the serial input
24
a
-
24
n
,
26
a
-
26
n
and/or
28
a
-
28
n
and passed through the selectable multiplexer
20
a
-
20
n
to the receive (RX) block
16
. The receive block
16
then passes the data to one of the parallel interfaces
15
a
-
15
n.
The selectable multiplexers
20
a
-
20
n
can be configured by management registers or by interface pins. When the connection from a particular port
14
a
-
14
n
for either transmit or receive needs to be changed, the configuration interface or the configuration registers pass this new information to the particular selectable multiplexers
20
a
-
20
b
. For the receive side, the receiver
16
has to wait for a period of time to acquire a lock.
The performance of the circuit
10
is significantly reduced since the amount of time to acquire a lock to a new port is of the order of the time it takes to send a block of data. Such a condition occurs in data communication switches.
SUMMARY OF THE INVENTION
The present invention concerns a method for receiving and transmitting one or more data packets comprising the steps of (A) receiving and transmitting the one or more data packets in response to one or more control signals and (B) generating the one or more control signals in response to the one or more data packets.
The objects, features and advantages of the present invention include providing a communication device that may (i) eliminate a lock time between successive transfers, (ii) improve the overall performance of the device, and/or (iii) conserve power.


REFERENCES:
patent: 4119805 (1978-10-01), Pratelli
patent: 4956839 (1990-09-01), Torii et al.
patent: 5101404 (1992-03-01), Kunimoto et al.
patent: 5247671 (1993-09-01), Adkins et al.
patent: 5251206 (1993-10-01), Calvignac et al.
patent: 5280591 (1994-01-01), Garcia et al.
patent: 5313591 (1994-05-01), Averill
patent: 5319754 (1994-06-01), Meinecke et al.
patent: 5321691 (1994-06-01), Pashan
patent: RE34896 (1995-04-01), Calvignac et al.
patent: 5408469 (1995-04-01), Opher et al.
patent: 5418781 (1995-05-01), Kaufman et al.
patent: 5428603 (1995-06-01), Kivett
patent: 5436893 (1995-07-01), Barnett
patent: 5438681 (1995-08-01), Mensch, Jr.
patent: 5440549 (1995-08-01), Min et al.
patent: 5440698 (1995-08-01), Sindhu et al.
patent: 5446726 (1995-08-01), Rostoker et al.
patent: 5450398 (1995-09-01), Abefelt et al.
patent: 5452259 (1995-09-01), McLaury
patent: 5459840 (1995-10-01), Isfeld et al.
patent: 5469545 (1995-11-01), Vanbuskirk et al.
patent: 5487170 (1996-01-01), Bass et al.
patent: 5499239 (1996-03-01), Munter
patent: 5504741 (1996-04-01), Yamanaka et al.
patent: 5537400 (1996-07-01), Diaz et al.
patent: 5546384 (1996-08-01), Dupuy et al.
patent: 5577032 (1996-11-01), Sone et al.
patent: 5577035 (1996-11-01), Hayter et al.
patent: 5579278 (1996-11-01), McLaury
patent: 5581713 (1996-12-01), Myers et al.
patent: 5583858 (1996-12-01), Hanaoka
patent: 5617367 (1997-04-01), Holland et al.
patent: 5634074 (1997-05-01), Devon et al.
patent: 5640675 (1997-06-01), Pinault et al.
patent: 5654968 (1997-08-01), Smiroldo
patent: 5668807 (1997-09-01), SChachar et al.
patent: 5673132 (1997-09-01), Carbone, Jr. et al.
patent: 5724351 (1998-03-01), Chao et al.
patent: 5724358 (1998-03-01), Headrick et al.
patent: 5787095 (1998-07-01), Myers et al.
patent: 5790539 (1998-08-01), Chao et al.
patent: 5793764 (1998-08-01), Bartoldus et al.
patent: 5799014 (1998-08-01), Kozaki et al.
patent: 5802052 (1998-09-01), Venkataraman
patent: 5835498 (1998-11-01), Kim et al.
patent: 5844887 (1998-12-01), Oren et al.
patent: 5850395 (1998-12-01), Hauser et al.
patent: 5852606 (1998-12-01), Prince et al.
patent: 5857111 (1999-01-01), Oda
patent: 5875190 (1999-02-01), Law
patent: 5912889 (1999-06-01), Preas et al.
patent: 5991295 (1999-11-01), Tout et al.
patent: 6215769 (2001-04-01), Ghani et al.
patent: 6246682 (2001-06-01), Roy et al.
patent: 6295295 (2001-09-01), Wicklund
patent: 6339596 (2002-01-01), Kozaki et al.

Affiliated with

Also associated with

Rating

Circuit, method and/or architecture for improving the... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit, method and/or architecture for improving the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit, method and/or architecture for improving the... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3066508