Circuit member for semiconductor device, semiconductor device us

Details Circuit member for semiconductor device, semiconductor device us Circuit member for semiconductor device, semiconductor device us

1998-01-26

2000-10-17

Picardat, Kevin M.

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

438108, 438111, 438123, H01L 2144, H01L 2148, H01L 2150

Patent

active

061330701

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to a circuit member for a surface mounting, plastic molded type semiconductor device having a circuit member thinly provided by plating, a semiconductor device using the circuit member, a process for producing the circuit member, and a process for producing the semiconductor device, particularly a circuit member for a plastic molded type BGA (ball grid array) type semiconductor device and a circuit member for a small package.


BACKGROUND ART

In recent years, for semiconductor devices, a tendency toward higher performance and reduction in thickness and size of electronic equipment have resulted in an ever-increasing demand for higher integration density and higher functions such as typified by ASIC (application-specific IC) of LSI.
In the semiconductor device having increased integration density and function, inductance within the package has become unnegligible for high-speed processing of signals. In order to reduce the inductance within the package, the number of connecting terminals of the power source and ground has been increased to lower the substantial inductance.
The higher integration density and higher function of the semiconductor device has resulted in increased total number of external terminals (pins) and an ever-increasing demand for an increase in number of terminals (pins).
In multi-terminal (pin) IC, particularly semiconductor devices, such as ASIC typified by gate array and standard cell, microprocessor unit, and DSP (digital signal processor), those using a lead frame include surface mounting type packages, such as QFP (quad flat package). In QFPs, the number of pins up to 300 pins has been put to practical use.
In QFPs, a single-layer lead frame 1310 as shown in FIG. 44b is used. As shown in FIG. 44a (cross-sectional view), a semiconductor element 1320 is mounted on a die pad 1311, an inner lead in its front end 1312A subjected to treatment, such as silver plating or gold plating, is connected to a terminal (an electrode pad) 1321 of the semiconductor element 1320 through a wire 1330, plastic molding is performed using a resin 1340, a dam bar section is cut, and an outer lead 1313 section is bent in a gull-wing form. In such QFP, the structure is such that an outer lead for electrical connection to an external circuit is provided in four directions of the package. This structure can cope with a demand for an increase in the number of terminals (pins). The single-layer lead frame 1310 used herein is generally prepared by fabricating a metal sheet having excellent electrical conductivity and high strength, such as Kovar, 42 alloy (42% Ni-iron), or copper-base alloy, by etching using photoetching, stamping or the like into a lead frame as shown in FIG. 44b.
A demand for an increase in signal processing speed and an increase in performance (function) of a semiconductor element in recent years, however, requires a further increase in number of terminals.
By contrast, in QFP, a reduction in external terminal pitch permits QFP to cope with a demand for a further increase in number of terminals. In the reduction in the external terminal pitch, however, the width of the external terminal per se should also be reduced, resulting in lowered external terminal strength. This unfavorably poses a problem associated with positional accuracy or flatness accuracy in molding of the terminal (formation of gull-wing). Further, in QFP, the step of mounting in a reduction in pitch becomes difficult with reducing the pitch of the outer lead to 0.4 mm, 0.3 mm or a smaller pitch, which necessitates realization of a highly advanced board mounting technique.
In order to avoid problems of mounting efficiency and mountability involved in the conventional QFP package, a plastic package semiconductor device called BGA (ball grid array), which is a surface mounting type package with the external terminal of the package being replaced by a solder ball, has been developed.
BGA is a generic name for a surface mounting type semiconductor device (plastic package) wherein the

REFERENCES:
patent: 5175060 (1992-12-01), Enomoto et al.
patent: 5497032 (1996-03-01), Tsuji et al.
patent: 5656550 (1997-08-01), Tsuji et al.
patent: 5759047 (1998-06-01), Brodsky et al.

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