Circuit-level memory and combinational block modeling

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation

Reexamination Certificate

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C703S002000, C703S013000, C703S014000, C703S020000, C703S021000, C703S022000, C716S030000, C341S106000

Reexamination Certificate

active

06968305

ABSTRACT:
A method and apparatus for creating a memory model for use in modeling a physical memory of an electronic circuit design. Memory write operations to the physical memory and memory read operations are modeled in a lookup table. The number of entries in the lookup table is limited by an upper bound representing a total number of memory operations that can occur over a given number of clock cycles.

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