Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2007-07-17
2007-07-17
Parker, Kenneth (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S776000, C257S773000, C257S786000, C257SE23141, C257SE23142, C257SE23143, C257SE23151, C257SE23152
Reexamination Certificate
active
10711281
ABSTRACT:
A circuit layout structure for a chip is provided. The chip has a bonding pad area, a nearby device area, and a substrate. The circuit layout structure essentially comprises a plurality of circuit layers, a plurality of dielectric layers and a plurality of vias. The circuit layers are sequentially stacked over the substrate. Each dielectric layer is sandwiched between a pair of adjacent circuit layers. The vias pass through the dielectric layers and electrically connect various circuit layers. The farthest circuit layer away from the substrate has pluralities of bonding pads within the bonding pad area. The bonding pads near the device area overstrides at least one non-signed circuit layer through the furthest circuit layer away from the substrate and electrically connects to a circuit layer nearer the substrate with vias. The circuit layout structure can avoid a direct conflict of signals between the power/ground circuits and the signal circuits.
REFERENCES:
patent: 5446243 (1995-08-01), Crowder et al.
patent: 6489689 (2002-12-01), Nojiri
patent: 6759329 (2004-07-01), Cheng et al.
patent: 2003/0011073 (2003-01-01), Shinogi et al.
Jiang Chyun IP Office
Karimy Mohammad Timor
Parker Kenneth
VIA Technologies Inc.
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