Active solid-state devices (e.g. – transistors – solid-state diode – Incoherent light emitter structure – In combination with or also constituting light responsive...
Reexamination Certificate
2000-07-14
2002-08-13
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Incoherent light emitter structure
In combination with or also constituting light responsive...
C257S084000, C257S431000, C257S577000
Reexamination Certificate
active
06433366
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit-incorporating light receiving device in which a photodiode for converting received light into an electrical signal and an integrated circuit for processing the converted signal are provided on a single silicon substrate, and to a method for fabricating the circuit-incorporating light receiving device.
2. Description of the Related Art
Circuit-incorporating light receiving devices are mainly used in optical pickups. For example, the circuit-incorporating light receiving devices detect a focus error signal which is in turn used to bring light of a semiconductor laser to a focus on a disk. Alternatively, the devices may detect a radial error signal which is in turn used to bring laser light to a pit on a disk (tracking). Recently, optical pickups are used in CD-ROM or DVD-ROM drives and the like which are becoming increasingly faster. There is a demand for a high-speed and high-performance circuit-incorporating light receiving device which may be used in such optical pickups.
FIG. 10
shows a conventional circuit-incorporating light receiving device
500
(Japanese Patent Publication No. 2731115) which has a split photodiode structure. A feature of the split photodiode structure shown in
FIG. 10
is that an N-type buried diffusion layer
103
and a P-type diffusion layer
109
are provided so as to reduce a diffusion current having a slow response. A semiconductor substrate
101
is made of P-type <
111
> 40 &OHgr;cm so as to reduce a junction capacitance. The use of such a material leads to expansion of a depletion layer, resulting in a decrease in a distance over which diffusing carriers having a low mobility are moved. For this reason, the response of a photodiode is improved. The photodiode portion of the device
500
attains a response of about 30 MHz as fc(−3 dB).
A silicon nitride film
111
as an antireflection film is further provided on the P-type diffusion layer
109
. The reflectance of the device
500
is thus reduced with respect to a laser wavelength of about 780 nm which is used for a CD-ROM.
In the integrated circuit portion of the circuit-incorporating light receiving device
500
, elements are isolated from each other using PN junction isolation. Arsenic (As+) and Boron (B+) are implanted into an emitter and a base, respectively, with ion implantation. A resulting NPN transistor has a fTmax of about 3 GHz. The integrated circuit portion of the device
500
attains a response of about 20 MHz.
Hereinafter, a fabrication process of the circuit-incorporating light receiving device
500
will be described with reference to
FIGS. 11A through 11H
.
On the P-type <
111
> 40 &OHgr;cm substrate
101
, as shown in
FIG. 11A
, a P-type buried diffusion layer
102
is provided in an isolation region and a region splitting the photodiode. The N-type buried diffusion layer
103
is provided in the photodiode portion for the purpose of improving the response of the split photodiode. The N-type buried diffusion layer
103
is provided in the NPN transistor portion. An N-type epitaxial layer
104
is provided on the buried diffusion layers
102
and
103
.
Next, as shown in
FIG. 11B
, a P-type diffusion layer
105
, a base region (not shown) of a vertical PNP (V-PNP) transistor, and a collector compensation diffusion layer
106
of the NPN transistor portion are provided.
Next, as shown in
FIG. 11C
, boron ion implantation provides the base region (internal base region
107
and external base region
108
) of the NPN transistor; the emitter region (not shown) of the V-PNP transistor; and the P-type diffusion layer
109
for improving the response of the split photodiode.
Next, as shown in
FIG. 11D
, an emitter region
110
of the NPN transistor is provided by arsenic ion implantation.
Next, as shown in
FIG. 11E
, a field silicon oxidization film is removed from a split photodiode light receiving region. The silicon nitride film
111
is provided on the split photodiode light receiving region by CVD. In this way, an antireflection film having the intended thickness can be obtained.
Next, as shown in
FIG. 11F
, a silicon oxidization film of a contact portion is etched. A first layer conductor
112
A made of AlSi is then provided by sputtering. A conductor portion
112
is provided by dry etching. In this case, a portion of AlSi which exists on the light receiving region of the split photodiode is not etched. The reasons are follows. The dry etching reduces the silicon nitride film
111
as the antireflection film. Plasma generated in the dry etching damages the photodiode, degrading the leakage characteristic of the photodiode.
Next, an interlayer insulating film
113
is provided and a through hole is provided in the integrated circuit. The interlayer insulating film
113
provided on the photodiode is removed by etching. As shown in
FIG. 11G
, an AlSi film is provided by sputtering and then patterned to provide a second layer conductor
114
while removing AlSi from the photodiode light receiving region.
Finally, as shown in
FIG. 11H
, the second layer conductor
114
and the split photodiode portion (first layer conductor
112
A and second layer conductor
114
) which are made of AlSi are etched by wet etching. Dry etching would reduce the silicon nitride film
111
as the antireflection film and degrades the leakage characteristic of the photodiode. Thereafter, a cover insulating film
115
is provided.
Thus, the circuit-incorporating light receiving element
500
shown in
FIG. 10
is obtained. Recently, there is a demand for a high-speed circuit-incorporating light receiving device. An attempt is made to achieve a high-speed split photodiode and a high-speed integrated circuit.
To obtain a higher-speed split photodiode, a CR time constant needs to be decreased. Specifically, photodiode capacitance Cpd or series resistance Rs needs to be decreased.
Japanese Laid-Open Publication No. 10-107243 proposes an exemplary structure of a photodiode shown in FIG.
12
. Such a structure provides the N-type buried diffusion layer
103
only on a portion which actually receives laser light from a semiconductor laser. This photodiode has a reduced junction area and thus achieves a reduction in junction capacitance while retaining the improved response due to the structure shown in FIG.
10
. In this case, in an area receiving light, there is a junction between the P-type diffusion layer
109
and the N-type epitaxial layer
104
. For this reason, a silicon thermal oxidation film
116
as an antireflection film is required. If a deposition film is provided directly on a silicon film by CVD or the like, there is an increased leakage current at the junction between the P-type diffusion layer
109
and the N-type epitaxial layer
104
, which are positioned at a surface portion. To avoid this, the silicon thermal oxidation film
116
is provided.
Each transistor needs to become fast to obtain a high-speed integrated circuit. In the case of an NPN transistor, for example, an effective way is to reduce the capacitance between the emitter and the base. To this end, impurity concentrations of the emitter and the base need to be decreased or an area between the emitter and the base needs to be decreased. However, the former strategy is not available because the carrier injection efficiency is reduced and the current amplification factor (hFE) is thus decreased.
To achieve a reduced area between the emitter and the base, an attempt is made to develop a lithography technique such that an alignment margin of a mask is reduced as much as possible. A structural approach is also made to minimize the area between the emitter and the base. For example, polycrystalline silicon which is doped with an N-type semiconductor such as arsenic is used as an emitter diffusion source (polycrystalline silicon emitter) or an electrode. In such a technique, emitter diffusion and the alignment margin of the contact are not necessary. The area between the emitter and the base thus can be re
Fukunaga Naoki
Kasamatsu Toshimitsu
Kubo Masaru
Ohkubo Isamu
Oka Mutsumi
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
Wilson Allan R.
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