Circuit including segmented switch array for capacitive...

Details Circuit including segmented switch array for capacitive... Circuit including segmented switch array for capacitive...

2000-05-16

2002-04-30

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

C327S538000

Reexamination Certificate

active

06380791

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to circuitry (including at least one segmented switch array) for reducing total load capacitance (including parasitic capacitance) at one or more nodes of an integrated circuit. In a class of embodiments, the invention is an analog integrated circuit which operates at high speed (in the sense that the potential at a node thereof varies rapidly) and has a segmented array of switches (rather than a conventional non-segmented array) coupled to the node, to reduce capacitive loading at the node.
2. Description of the Related Art
In integrated circuits, a large total load capacitance at one node can pose a potential stability problem, especially in cases in which the integrated circuit has an analog design and operates at high speed (in the sense that the potential at the node varies rapidly over time). A large total load capacitance can result from parasitic capacitances that add up to a significant amount of capacitance, or it can result from a large capacitor in the design.
Analog integrated circuits that operate at high speed (as well as other integrated circuits) are subject to the problem of large parasitic capacitances, especially at nodes where the potential varies rapidly as a function of time. For example, in an integrated circuit including the conventional multiple-gain block shown in
FIG. 1
, node A is subject to the problem of large parasitic capacitance. In
FIG. 1
, amplifier
1
has a first input coupled to receive input potential “Vin,” a second input (Node A) coupled to switches S
1
-S
x
(where “x” is an integer greater than three), and an output (at which the amplifier asserts output potential “Vout”). Switch S
1
is coupled between Nodes A and B
1
, switch S
2
is coupled between Nodes A and B
2
, switch S
3
is coupled between Nodes A and B
3
, switch S
x
is coupled between Node A and Node Bx, switches S
4
through S
x−1
(if present) are coupled in parallel between Node A and nodes between Nodes B
3
and Bx, resistor R
1
is coupled between Nodes B
1
and B
2
, resistor R
2
is coupled between Nodes B
2
and B
3
, resistors R
3
through R
x−1
(if present) are coupled in series between Nodes B
3
and Bx, and resistor R
x
is coupled between Node Bx and either the bottom rail or some quiet DC level. The array of switches and resistors causes amplifier
1
to output any selected one of multiple values of output voltage Vout at the amplifier's output node.
Many variations on the
FIG. 1
design are possible, including variations with only two or three switches connected in parallel between the amplifier and the series-connected resistors.
FIG. 2
is a schematic diagram of an NMOS transistor which implements each of switches S
1
-S
x
(of
FIG. 1
) in a typical implementation of FIG.
1
. The control signal for the switch (“CONTROL”) is asserted to the gate of the NMOS transistor. The NMOS transistor of
FIG. 2
has a parasitic gate-to-source capacitance (which is indicated by the symbol C
gs
in FIG.
2
).
Some designs require only N-channel switches (switches implemented as NMOS transistors) but most others require switches implemented as transmission gates (each including an NMOS and a PMOS transistor) for good transfer of signals.
FIG. 3
is a schematic diagram of such a transmission gate, consisting of an NMOS transistor and a PMOS transistor coupled together as shown (with the drain of the NMOS transistor connected to the source of the PMOS transistor, and the source of the NMOS transistor connected to the drain of the PMOS transistor), which can be used to implement each of switches S
1
-S
x
(of
FIG. 1
) in another typical implementation of FIG.
1
. The control signal for the switch (“CONTROL”) is asserted to the gate of the NMOS transistor, and the inverse of the control signal (“−CONTROL”) is asserted to the PMOS transistor's gate. In
FIG. 3
, the NMOS transistor has a parasitic gate-to-source capacitance (indicated by the symbol C
gsn
in
FIG. 3
) and the PMOS transistor has a parasitic gate-to-drain capacitance (indicated by the symbol C
gsp
in FIG.
3
). Typically, C
gs
, C
gsn
and C
gsp
are not equal, and a switch implemented as in
FIG. 3
has at least twice the parasitic capacitance of a switch implemented as in FIG.
2
.
FIG. 4
is a lumped equivalent model of the
FIG. 1
circuit. The total capacitance of the switches S
1
-S
x
(which is the sum of the parasitic capacitances C
gs
of transistors implementing them) at node A is represented as lumped capacitance C
lumped
in FIG.
4
.
Writing the Kirchoff's Current Law equation at node A gives
Vin
·
[
1
R
1
+
1
R
2
+
s
·
Clumped
]
=
Vout
·
[
1
R
2
]
where R
2
represents the resistance between Node A and the amplifier's output node, R
1
represents the resistance between Node A and the bottom rail (or other node at a quiet DC level), and “s” has units of frequency.
Solving for Vin/Vout gives
Vin
Vout
=
[
R
1
(
R1R2Clumped
)
s
+
(
R1
+
R2
R1R2Clumped
)
]
The form of the denominator of this transfer function
⟩
s
+
R1
+
R2
R1R2Clumped
⟨
implies that there is a pole located at
wp
=
-
[
R1
+
R2
R1R2Clumped
]
The pole frequency is
fp
=
-
1
2
⁢
 
⁢
π
·
[
R1
+
R2
R1R2Clumped
]
It can be seen from
FIG. 1
that if there are too many switches S
1
-S
x
, there can be significant capacitive loading at node A of the amplifier.
With reference to FIG.
1
and its equivalent (FIG.
4
), due to the presence of the pole related to the lumped capacitance C
lumped
(where C
lumped
depends on the parasitic capacitances of the switches of the
FIG. 1
circuit), if the number of gain steps in an implementation of the
FIG. 1
circuit is large (i.e., if the index “x” is large), and the lumped capacitance C
lumped
is large, the pole can be at a low enough frequency so that it interferes with the transient response of the amplifier. This interference can cause ringing of the amplifier and can result in nonlinearities in the system, thus degrading the systems S-to-N performance (where “S” represents signal and “N” represents noise plus distortion).
In accordance with the present invention, a switch array (coupled to a node of an integrated circuit) is implemented in such a way as to reduce the total load capacitance at the node (including by reducing the parasitic capacitances of the switches), thereby reducing the problems (noted in the preceding paragraph) which would otherwise result from conventional implementation of the switch array.
SUMMARY OF THE INVENTION
In a class of embodiments, the invention is an integrated circuit having at least one node at which the potential varies with time (during operation) and which is the root node of a segmented array of switches. In some embodiments, the circuit includes a single segmented array of switches. In other embodiments, the circuit includes a least two segmented arrays of switches (each having a different root node).
Each segmented switch array comprises switches connected between nodes having a tree structure. The nodes include the root node and additional nodes of at least two different degrees (D) relative to the root node. The array has at least two primary segments (each including a switch and a node of degree D=1) connected in parallel between the first node and additional circuitry (or a second node). At least one primary segment has multiple secondary segments (each including a switch and a node of degree D=2) connected in parallel between one of the nodes of degree D=1 and the additional circuitry (or second node).
By providing a segmented array (rather than a non-segmented array) of switches at a node, the total load capacitance (including parasitic capacitance) at the node is reduced in accordance with the invention. In some embodiments, the invention is an analog integrated circuit which operates at high speed (in the sense that the circuit has a first node at which the potential varies rapidly) and which has a segm

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