Circuit including a subtractor, an adder, and first and second c

Details Circuit including a subtractor, an adder, and first and second c Circuit including a subtractor, an adder, and first and second c

1995-06-07

1996-09-03

Chin, Stephen

Pulse or digital communications

Receivers

Interference or noise reduction

36472401, H04B 110

Patent

active

055531032

ABSTRACT:
A digital filter circuit includes a first input for samples of a digital signal, a subtractor, an adder and a first clocked register connected in series. The first input of the circuit is connected to the minuend input of the subtractor and the output of the first clocked register is connected to the subtrahend input of the subtractor. The second clocked register connected in series at a position between the output of the subtractor and a first input of the adder stores the difference from the subtractor or a value proportional to it. A third clocked register latches the value in the first clocked register and supplies it as a second input to the adder. The filtered output is taken from the first or third register. The circuit optionally includes a scaler connected in series between the output of the subtractor and the first input of the adder. The scaler optionally operates by shifting the digits to positions of less significance. The circuit optionally has a second input and a multiplexer connected to supply alternately to the subtractor samples from the first circuit input and samples from the second circuit input. The second circuit input is connected to the output of the second clocked register, thereby forming two digital filter circuits in a time division manner. The multiplying factor of the scaler may be switchable to alternate between first and second values for providing different filter characteristics.

REFERENCES:
patent: 4313173 (1982-01-01), Candy et al.
patent: 4607281 (1986-08-01), Starck
patent: 5142377 (1992-08-01), Moriyama et al.

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