Boots – shoes – and leggings
Patent
1993-04-14
1995-05-30
Kim, Ken S.
Boots, shoes, and leggings
3642292, 3642476, 3642616, 3642632, 3642701, 364DIG1, 3649411, 3642302, 3642628, 395375, G06F 922
Patent
active
054210216
ABSTRACT:
A method of handling a fault associated with a first floating point instruction upon reaching the next sequential floating point instruction is described. The first floating point instruction is decoded. A first floating point microinstruction received from a control memory is stored in a first latching means and in a second latching means. The next sequential floating point instruction is decoded. There is a jump to a plurality of exception handler microinstructions stored in the control memory, the jump occurring upon the detection of the fault associated with first floating point instruction. The plurality of exception handler microinstrictions includes an exception handler floating point microinstruction. The exception handler floating point microinstruction received from the control memory is stored in the first latching means, replacing the previous microinstruction stored in the first latching means. The exception handling floating-point microinstruction received from the control memory is not stored in the second latching means. The exception handler floating point microinstruction stored in the first latching means is executed. The floating point microinstruction stored in the second latching means is executed. A method for allowing floating point instructions to be executed in a microprocessor in parallel with non-floating point instructions is also described. Circuitry allowing floating point instructions to be executed in parallel with non-floating point instructions is also described.
REFERENCES:
patent: 4179737 (1979-12-01), Kim
patent: 4398244 (1983-08-01), Chu et al.
patent: 4429361 (1984-01-01), Maccianti et al.
patent: 4438492 (1984-03-01), Harmon, Jr. et al.
patent: 4476523 (1984-10-01), Beauchamp
patent: 4598356 (1986-07-01), Dean et al.
patent: 4719565 (1988-01-01), Moller
patent: 4750110 (1988-06-01), Mothersole et al.
patent: 4758950 (1988-07-01), Cruess et al.
patent: 4763294 (1988-08-01), Fong
patent: 4791551 (1988-12-01), Garde
patent: 4901235 (1990-02-01), Vora et al.
patent: 4912635 (1990-03-01), Nishimukai et al.
patent: 4928223 (1990-05-01), Dao et al.
patent: 5043867 (1991-08-01), Bhandarkar et al.
patent: 5095426 (1992-03-01), Senta
patent: 5109514 (1992-04-01), Garner
Intel Corporation
Kim Ken S.
LandOfFree
Circuit including a latching unit for holding instructions durin does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit including a latching unit for holding instructions durin, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit including a latching unit for holding instructions durin will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-370034