Circuit implementations for asynchronous processors

Details Circuit implementations for asynchronous processors Circuit implementations for asynchronous processors

1997-11-25

2000-11-28

Teska, Kevin J.

G06F 1500

Patent

active

061526134

ABSTRACT:
An asynchronous and delay-insensitive data processor comprises a plurality of components communicating with each other and synchronizing their activities by communication actions on channels and buses. Each component consists of a control part and a data part. All control parts are implemented with a lazy-active-passive handshake protocol and a sequencing means called a left/right buffer that provides the minimal sequencing constraints on the signals involved. The data parts comprise novel asynchronous ALU, buses, and registers. The control parts and data parts are connected together in an asynchronous and delay-insensitive manner.

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