Circuit implementation to quench bit line leakage current in pro

Details Circuit implementation to quench bit line leakage current in pro Circuit implementation to quench bit line leakage current in pro

1999-10-13

2000-04-04

Tran, Andrew Q.

Static information storage and retrieval

Floating gate

Disturbance control

36518512, 36518513, 3651853, 36518533, G11C 1612, G11C 1616

Patent

active

060469323

ABSTRACT:
A method of and a flash memory device for quenching bitline leakage current during programming and over-erase correction operations. The flash memory cells are organized in an array of I/O blocks with each block having columns and rows. An array of resistors is connected between the common array source connection and ground. The array of resistors is made up of sets of resistors, each set having a programming mode resistor and an APDE mode resistor. A data buffer switches either a programming mode resistor or APDE mode resistor into the circuit when a bitline is selected for either programming or APDE. The values of the resistors are selected to raise the voltage at the source above a selected threshold voltage of the memory cells so that over-erased cells will not provide leakage current to the bitline during either programming or APDE.

REFERENCES:
patent: 5642311 (1997-06-01), Cleveland et al.

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