Miscellaneous active electrical nonlinear devices – circuits – and – Specific input to output function – Combining of plural signals
Reexamination Certificate
2000-11-28
2002-09-24
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific input to output function
Combining of plural signals
C327S358000, C327S361000
Reexamination Certificate
active
06456142
ABSTRACT:
BACKGROUND
A prior art analog multiplier is shown in block diagram form in FIG.
1
and in more detailed schematic form in FIG.
2
. Referring to
FIG. 1
, the circuit includes a translinear multiplier core
10
which is driven by two identical input amplifiers
12
and
14
. The input amplifiers are transconductance (gm) stages which convert the input voltages V
X
and V
Y
into currents I
X
and I
Y
. The multiplier core generates an output current I
OUT
proportional to the product of V
X
and V
Y
divided by a scale factor SF:
I
OUT
=
(
V
X
V
Y
SF
)
(
Eq
.
1
)
Referring
FIG. 2
, the translinear multiplier core is implemented as a pair of emitter-coupled transistors Q
3
, Q
4
which are preceded by a classic arrangement of pre-distortion diodes Q
1
and Q
2
that predistort the X input signal so as to compensate for the hyperbolic tangent (tanh) characteristic of the emitter-coupled pair, thereby extending the linear input range. For simplicity, the input amplifiers
12
and
14
are not shown in FIG.
2
. Instead, the “X” input is shown generically as (1−X)I
X
and (1+X)I
X
, where X is a modulation factor that varies between −1 and +1. The “Y” input is shown as the current (1−Y)I
Y
, where Y varies between −1 and +1.
The circuit shown in
FIGS. 1 and 2
suffers from several sources of error. Although these errors have been analyzed in detail in B. Gilbert, “A Precise four-quadrant multiplier with subnanosecond response,”
IEEE J. Solid State Circuits
, vol. SC-3, pp. 365-373, December 1968, a few will be summarized here. First, any mismatch in the emitter area ratios of Q
1
through Q
4
causes even-order distortion. More specifically, if A
1
through A
4
are the emitter areas of Q
1
through Q
4
, respectively, then there is no distortion in the ideal case where:
A
1
A
2
·
A
4
A
3
=
1
(
Eq
.
2
)
Any inaccuracy in area the area ratios, however, causes even-order distortion as shown in FIG.
3
. The solid line in
FIG. 3
illustrates the ideal output characteristic of I
OUT
for a given value of Y, as X is swept from −1 to +1, whereas the broken line shows the actual output characteristic when there is a mismatch in the emitter area ratios.
An additional source of error is the ohmic resistance associated with transistors Q
3
and Q
4
. This introduces odd-order distortion as shown in
FIG. 4
, where the solid line shows the ideal output characteristic, and the broken line shows the actual output characteristic caused by the ohmic resistances of the transistors.
Another source of error is the distortion introduced by the gm stages used to convert the input voltages to currents.
FIG. 5
illustrates a typical gm stage used to generate the input currents to the translinear multiplier. The circuit of
FIG. 5
is shown configured to generate the (1−Y)I
Y
input to the translinear multiplier (the (1+Y)I
Y
output from Q
6
is diverted to ground), but an identical circuit could also be used generate the “X” inputs as well. Curves
13
,
15
and
17
in
FIG. 6
illustrate the incremental gain of this gm stage for increasing values of the emitter resistor R
Y
, respectively. From
FIG. 6
, it is apparent that the curvature of the incremental gain near the gain axis can be reduced, and therefore, the linearity improved, by increasing the value of R
Y
. However, this also reduces the sensitivity of the gm stage and introduces a noise penalty because R
Y
is a significant noise generator. Moreover, the non-linearity of this stage is never completely eliminated.
A well-known technique for reducing the distortion of a circuit element is to close a negative feedback path around the element. A prior art circuit that attempts to use feedback in the context of a multiplier is shown in block diagram form in FIG.
7
and in more detailed schematic form in FIG.
8
. Referring to
FIG. 7
, a third input amplifier
16
for receiving a “Z” input has been added to the circuit of
FIG. 1. A
high gain amplifier
18
nulls the output from the multiplier core and the output from the Z amplifier (attenuated by network
19
) to produce the final output signal V
OUT
. The output signal is fed back to the Z amplifier through a feedback path including resistors R
1
and R
2
.
Because the X, Y, and Z input amplifiers
12
,
14
, and
16
are identical, the circuit of
FIGS. 7 and 8
reduces the distortion introduced by the X and Y amplifiers. This circuit does not, however, reduce the distortion introduced by the multiplier core because the feedback path is not closed around the multiplier core. If the final output signal V
OUT
is fed back to the Y input amplifier in an effort to close the feedback loop around the multiplier core as shown in
FIG. 9
, the circuit ceases to function as a multiplier. Instead, it behaves as a divider with the Z input providing the numerator and the X input providing the denominator:
V
OUT
=
SF
·
(
V
X
+
-
V
X
-
)
(
V
Z
-
-
V
Z
+
)
(
Eq
.
3
)
A further problem with such a feedback arrangement is that the bandwidth is now proportional to the magnitude of the denominator as shown in FIG.
10
. That is, bandwidth is obtained at the expense of gain, as is well-known when utilizing negative feedback.
Another aspect of the multiplier circuits described above is that the gain is only well-defined at the minimum end of the gain range, but the maximum gain is not defined. That is, when the Y input is zero, the output is zero for any value of the X input, but as the Y input increases, the gain continues to increase indefinitely. There are applications, however, where a well-defined maximum gain is useful, as for example, with a video keyer.
REFERENCES:
patent: 4006353 (1977-02-01), Pierce
patent: 4156283 (1979-05-01), Gilbert
patent: 4586155 (1986-04-01), Gilbert
patent: 4894845 (1990-01-01), Jansenn et al.
patent: 5157350 (1992-10-01), Rubens
patent: 5187682 (1993-02-01), Kimura
patent: 5389840 (1995-02-01), Dow
patent: 5650743 (1997-07-01), Bien et al.
patent: 5659263 (1997-08-01), Dow et al.
patent: 5925094 (1999-07-01), Kimura
patent: 6255889 (2001-07-01), Branson
A New Wide-Band Amplifier Technique by Barrie Gilbert, IEEE J. Solid-State Circuits, vol. SC-3, pp. 353-365, Dec. 1968;.
A High-Performance Monolithic Multiplier Using Active Feedback by Barrie Gilbert, IEEE J. Solid-State Circuits, vol. SC-9, No. 6, pp. 364-373, Dec. 1974.
Data sheet for Internally Trimmed Precision IC Multiplier AD534 by Analog Devices, pp. 1-12, 1999.
Data sheet for 60 MHz, 2000 V/&mgr;S Monolithic Op Amp AD844 by Analog Devices, pp. 1-12, 1990.
The current conveyor: history, progress and new results by A.S. Sedra, G.W. Roberts and F. Gohn, IEE Proceedings, vol. 137, Pt. G, No. 2, Apr. 1990.
Analog Devices Inc.
Callahan Timothy P.
Marger & Johnson & McCollom, P.C.
Nguyen Hai L.
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