Circuit having delay locked loop for correcting off chip...

Details Circuit having delay locked loop for correcting off chip... Circuit having delay locked loop for correcting off chip...

2007-04-03

2007-04-03

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C713S400000

Reexamination Certificate

active

10974521

ABSTRACT:
A circuit comprises an off chip driver and a delay locked loop. The delay locked loop is configured to receive a clock signal and provide a first signal for compensating for a rising edge propagation delay through the off chip driver and a second signal for compensating for a falling edge propagation delay through the off chip driver. The off chip driver is configured to receive the first signal and the second signal and output data aligned with the clock signal.

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patent: 6137327 (2000-10-01), Schnell
patent: 6313674 (2001-11-01), Akita et al.
patent: 6337834 (2002-01-01), Isobe et al.
patent: 6396322 (2002-05-01), Kim et al.
patent: 6696872 (2004-02-01), Le et al.
patent: 6704881 (2004-03-01), Li et al.
patent: 6934215 (2005-08-01), Chung et al.
patent: 6968026 (2005-11-01), Li et al.

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