Circuit having combined level conversion and logic function

Details Circuit having combined level conversion and logic function Circuit having combined level conversion and logic function

1995-09-22

1997-04-22

Nelms, David C.

Static information storage and retrieval

Associative memories

Ferroelectric cell

36518907, 3652256, G11C 700

Patent

active

056234376

ABSTRACT:
A circuit having a combined level conversion and logic function (37, 90, 101, 102, and 103) receives a differential CMOS level input signal, and an input signal having a relatively small logic swing, performs a logic operation, and provides a single-ended CMOS output signal. The circuit (37) includes a CMOS switching portion (71) and a small signal switching portion (75) connected to provide a CMOS output signal that is the result of a logical operation of the input signals. The circuits (37, 90, 101, 102, and 103), eliminate the need for a separate level converter, reducing at least a gate delay, and insuring faster generation of the output signal. Also, the use of the circuit (37) having a combined level conversion and logic function allows the cache TAG (20) to provide read data at the same time that a match signal is generated.

REFERENCES:
patent: 4907189 (1990-03-01), Branson et al.
patent: 5218567 (1993-06-01), Suzuki
patent: 5289414 (1994-02-01), Hatsuda
patent: 5301148 (1994-04-01), Okajima
patent: 5473561 (1995-12-01), Jones

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