Circuit having a master-and-slave and a by-pass

Details Circuit having a master-and-slave and a by-pass Circuit having a master-and-slave and a by-pass

1992-12-16

1995-01-03

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327208, H03K 3289, H03K 1756

Patent

active

053789342

ABSTRACT:
Because a bypass circuit BP connected in parallel with serial paths of first and second storage circuits MF and SF has less serially-connected stages of gates incorporated therein than the storage circuits and has shorter information transfer delay of input data to an output terminal 21 than the storage circuits, the bypass circuit BP outputs the information to the output terminal before the outputs of the storage circuits are determined when data supplied to a data input terminal 20 is fetched synchronously with a clock signal CK. The first and second storage circuits MF and SF are master/slave-operated in diagnosis mode, and the output operation of the bypass circuit BP is inhibited according to the states of signals C1 and C2 for controlling their master/slave operations regardless of the clock change of the first control signal CK. Thus, the master/slave operations of the first and second storage circuits MF and SF are assured in the diagnosis mode.

REFERENCES:
patent: 3917961 (1975-11-01), Reed
patent: 4409680 (1983-10-01), Schnathorst et al.
patent: 4584489 (1986-04-01), Tanaka
patent: 4780890 (1988-10-01), Kane
patent: 4970407 (1990-11-01), Patchen
patent: 5023475 (1991-06-01), Ducourant
patent: 5028814 (1991-07-01), Sung et al.
patent: 5049760 (1991-09-01), Oooms
patent: 5095225 (1992-03-01), Usui
patent: 5148052 (1992-09-01), Yellanilli
"Second Generation Floating-Point Arithmetic Coprocessor with a 32-Bit Bus," Nikkei Electronics, Jul. 13, 1987, pp. 123-138.

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