Electricity: power supply or regulation systems – Self-regulating – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2001-08-01
2003-06-24
Nelms, David (Department: 2818)
Electricity: power supply or regulation systems
Self-regulating
Using a three or more terminal semiconductive device as the...
C323S315000
Reexamination Certificate
active
06583611
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a circuit generating a voltage signal which is independent of temperature and has low sensitivity to variations in process parameters.
More particularly, the invention relates to a circuit comprising at least an output MOS transistor, through which an output current flows, being connected to a first voltage reference, and having a gate terminal connected to a bias network connected between a second voltage reference and said first voltage reference.
2. Description of the Related Art
In order to generate a signal which is independent of temperature and has low sensitivity to process parameter variations, temperature-independent current generators have been used, which charge and discharge a capacitor.
In order to provide such a current generator, the current-voltage characteristic I
D
(Vgs) of a MOS transistor is used. As schematically illustrated in
FIG. 1
, a reference voltage Vgsx can always be found at which the current I
DX
flowing through a MOS transistor will not vary with temperature T.
In particular,
FIG. 1
illustrates the current-voltage characteristic of a MOS transistor at three different temperatures T1, T2 and T3. This characteristic shows a zero-temperature-coefficient point X at the reference voltage Vgsx where the current I
D
does not vary with temperature.
Thus, by applying such a bias voltage Vgsx between the gate and source terminals of a MOS transistor, the transistor is led to conduct a temperature-independent current I
DX
between the source and drain terminals.
In particular, the current I
D
, or drain current, which flows through a MOS transistor operating in its linear region, is given by:
I
D
=
1
2
·
μ
·
Cox
·
W
L
·
(
Vgs
-
Vth
)
2
=
1
2
·
μ
·
Cox
·
W
L
·
Δ
V
2
(
1
)
where: &mgr; is electron mobility; Cox is the capacitance of silicon oxide; Vgs is the bias voltage of the gate terminal, that is, the voltage applied between the gate and source terminals; and Vth is the transistor threshold voltage.
Those parameters which vary appreciably with the temperature T are the mobility &mgr; and the threshold voltage Vth, while the variation of the capacitance Cox is negligible.
In particular, the threshold voltage Vth is known to decrease almost linearly as the temperature T increases, this variation obeying the following equation:
Vth
(
T
)=
Vth
(
T
0
)+
CT
MOS
·(
T
-
T
0
) (2)
where CT
MOS
is the thermal coefficient of the MOS transistor and T
0
is room temperature.
Thus, the term depending on the voltage variation, &Dgr;V
2
, increases in equation (1) as the square of the change in temperature T.
Also, the mobility &mgr;, as a function of the temperature T, obeys the following equation:
μ
(
T
)
=
μ
0
·
(
T
T
0
)
-
α
(
3
)
where &agr; is a coefficient with a value in the range of 1.5 to 2.
The zero-temperature-coefficient point X in the diagram of
FIG. 1
, where the current I
D
and the voltage Vgs are independent of the temperature T, is analytically calculated by assuming that the first derivatives of those functions which represent the values of I
D
and Vgs with respect to the temperature T are simultaneously zero.
If ∂I
D
(
T
)/∂
T=
0, then:
Vgs
(
t
)
=
2
·
T
α
·
(
∂
Vgs
(
T
)
∂
T
-
CT
MOS
)
+
Vth
(
T
0
)
+
CT
MOS
·
(
T
-
T
0
)
(
4
)
Now, if ∂
Vgs
(
T
)/∂
T=
0, then:
&agr;=2
In conclusion, there exists a point where, once an appropriate voltage Vgs is set, the current I
D
flowing through a MOS transistor does not vary with temperature if the coefficient &agr; equals 2.
However, the variation of the current I
D
with the temperature T is quite small when the coefficient &agr; is between 1.5 and 2.
As for the variations related to the manufacturing process of the MOS transistor, it is well known that the threshold voltage Vth and the capacitance Cox are appreciably affected by such variations, causing the current I
D
to also become dependent on process variations.
On the other hand, the mobility &mgr; varies very little with the variations in process parameters; it primarily depends on the dopant element, and can be set with an accuracy of within 5%, so that the mobility &mgr; is one of the best controlled parameters.
Thus, it is necessary to compensate the error introduced by the capacitance Cox variation, or the variation in the thickness of the gate oxide, and by the threshold voltage Vth variation.
If the capacitor C
1
dielectric is formed using the gate oxide layer of the MOS transistor, variations in the capacitance Cox are compensated by the capacitor C
1
, thus reducing its dependence on the process parameter variations.
As for the threshold voltage Vth of the MOS transistor, a circuit configuration, connected to the capacitor C
1
and the MOS transistor functioning as a current generator, is used in order to force the transistor to operate at the calculated zero-temperature-coefficient point X to decrease its dependence on temperature.
A known circuit that generates a constant voltage signal is generally shown at
1
in
FIG. 2
, in schematic form.
The circuit
1
comprises a capacitor C
1
connected between a first supply voltage reference Vcc and a constant current generator
2
, the circuit
1
basically consisting of a MOS transistor M
out
and a bias network
3
.
The transistor M
out
has a gate terminal G connected to the bias network
3
, a drain terminal D connected to a terminal of the capacitor C
1
to form an output terminal OUT, and a source terminal S connected to a second voltage reference, specifically a ground reference GND.
The voltage Vout at the node OUT, therefore, depends on the charged state of the capacitor C
1
.
The bias network
3
comprises first M
1
and second M
2
MOS transistors connected in a diode configuration, that is, each with its respective gate and drain terminals connected, these transistors being connected in series between the supply voltage Vcc and ground GND references. In particular, the first transistor M
1
is connected to the supply voltage reference Vcc through a current mirror
4
.
The current mirror
4
is further connected to the ground reference GND through a series of a first bipolar transistor Q
1
and a first resistive element R
1
, the latter comprising a resistor pair R
1
a
and R
1
b.
The second transistor M
2
is further connected to the ground reference GND through a second resistive element R
2
, the latter comprising a resistor pair R
2
a
and R
2
b.
The bias network
3
also includes a third MOS transistor M
3
, connected between the supply voltage reference Vcc and the gate terminal G of the transistor Mout, the latter connected to the ground reference GND through a second bipolar transistor Q
2
and a third resistive element R
3
connected in series.
The third transistor M
3
has a gate terminal connected to the gate terminal of the first transistor M
1
.
Finally, the first Q
1
and second Q
2
bipolar transistors have base terminals in common and connected to a bias voltage reference Vpol.
As shown in
FIG. 2
, the current mirror
4
particularly comprises fourth Q
4
, fifth Q
5
and sixth Q
6
bipolar transistors which are connected to the supply voltage reference Vcc through fourth R
4
, fifth R
5
and sixth R
6
resistive elements, respectively.
The fourth bipolar transistor Q
4
is further connected to the first bipolar transistor Q
1
, and has a base terminal connected to the base terminal of the fifth bipolar transistor Q
5
, the latter in turn connected to the first MOS transistor M
1
.
The sixth bipolar transistor Q
6
is connected to the ground reference GND, and has a base terminal connected to the first bipolar transistor Q
1
.
The operation of the circuit
1
shown in
FIG. 2
will now be discussed.
The bias network
3
essentially functions to bias the MOS transistor M
OUT
at the point where, with
de Guzman Dennis M.
Jorgenson Lisa K.
Le Thao P
Nelms David
Seed IP Law Group PLLC
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