Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-12-21
2003-04-22
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
Reexamination Certificate
active
06552602
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit generating a stable reference voltage with respect to temperature.
The invention relates, particularly but not exclusively, to a circuit generating a stable reference voltage with respect to temperature for CMOS process, the detailed description that follows covering this field of application for convenience of explanation only.
2. Description of the Related Art
As is well known, a requirement of most integrated electronic circuits is that at least one reference voltage be generated internally of the semiconductor chip in which they have been integrated.
An example of reference voltages internally generated a chip are VCM reference voltages having levels intermediate between the supply voltage values and being intended for use by several circuit sections integrated in the chip.
In particular, these internally generated reference voltages should be stable with respect to temperature and be unaffected by possible variations in the supply voltages, such as variations caused by rippling on the supply lines.
To provide a voltage reference that be unaffected by ripple, an internal reference voltage is normally used which is already provided in the chip structure.
In a typical P-substrate CMOS process, this internal reference voltage would be the base-emitter voltage Vbe of a parasitic PNP bipolar transistor created in the integrated circuit during the process.
This voltage actually exhibits a degree of dependence on temperature that can be eliminated, at least as concerns its first order component, by adding a compensating voltage to it, the latter voltage being quite easily obtained across a resistor through which an appropriate current flows.
More particularly, since the base-emitter voltage Vbe has a negative temperature coefficient, the compensating voltage is adjusted to have a positive temperature coefficient.
A simple known type of circuit adapted to generate such a reference voltage, compensated for temperature variations, is that shown generally and schematically at
1
in FIG.
1
.
In particular, the generator circuit
1
comprises a bipolar transistor T
1
, specifically of PNP type, which is connected between a first voltage reference, e.g., a supply voltage Vcc, and a second voltage reference, e.g., a ground reference GND. In the instance of the integrated circuit that contains the voltage generator being formed with CMOS technology, a parasitic transistor may be utilized as transistor T
1
.
The bipolar transistor T
1
has a first conduction terminal, which may be the collector terminal, connected to ground GND; a second conduction terminal, which may be the emitter terminal, connected to an internal circuit node X
1
; and a control terminal, i.e., the base terminal, connected to the first conduction terminal and ground.
This internal circuit node X
1
is connected to the supply voltage reference Vcc through a series of a resistive element R
1
and a generator G
1
generating a current I
1
. The reference voltage Vref sought is picked off an output terminal OUT
1
of the generator circuit
1
, between the resistive element R
1
and the generator G
1
.
To compensate for the thermal dependence of the base-emitter voltage Vbe of the bipolar transistor T
1
, the generator G
1
supplies a current I
1
having a positive coefficient of dependence on temperature.
As the skilled persons in the art know well, such a current value may be obtained by making use of a pair of parasitic bipolar transistors, biased to different current densities, from which a base-emitter voltage difference &Dgr;Vbe is derived for application to a resistive element of resistance R, so as to obtain a current:
I
1
=&Dgr;
Vbe/R.
The current I
1
thus obtained has a positive coefficient of dependence on temperature, and the reference voltage Vref at the output terminal OUT
1
is, therefore, compensated for temperature.
It should be noted that in most cases, a current having these characteristics would be already provided in analog integrated circuits of the CMOS type, where it is used for biasing operational amplifiers, for example.
However, in such circuits, the reference voltage Vref, also known as the band-gap voltage, has in practice to approach the band-gap voltage of the silicon layer in which the whole circuitry is formed, in order to achieve good compensation of the temperature coefficients. This voltage is a physical constant that depends on the type of semiconductor employed, it being approximately 1.2 V for silicon.
Thus, the generator circuit
1
of
FIG. 1
cannot provide reference voltages Vref that arestable with respect to temperature but displaced from the value of the band-gap voltage (1.2 V) for silicon. It is sometimes necessary, however, to have temperature-stable reference voltages generated which lie far from this value.
A prior approach to meeting this requirement is shown schematically in FIG.
2
.
In particular,
FIG. 2
shows a circuit
2
generating a stable voltage with respect to temperature, which circuit comprises essentially an operational amplifier OA
2
having a first non-inverting (+) input terminal connected to a band-gap circuit BG
2
adapted to supply the operational amplifier OA
2
with a stable reference voltage with respect to temperature, Vref of about 1.2 V, same as in the prior approach just described.
The operational amplifier OA
2
is in a buffer configuration having a first resistive element R
21
connected between an output terminal and an inverting (−) input terminal of the amplifier OA
2
, and a second resistive element R
22
connected between the inverting (−) input terminal and a voltage reference, e.g. a ground reference GND.
The generator circuit
2
uses the operational amplifier OA
2
to convert the resulting stable voltage Vref=1.2 V provided by the band-gap circuit BG
2
into another voltage KVref, where K is the gain of the buffer comprising the operational amplifier OA
2
.
In this way, any stable voltage value other than the band-gap value (equal approximately to 1.2 V) of the silicon layer can be derived from the temperature-stable voltage Vref.
To achieve values of the coefficient K greater than 1, the operational amplifier OA
2
must be used in the non-inverting configuration.
While on several counts advantageous, there are drawbacks to this approach, among which:
an operational amplifier OA
2
must be added to the chip own circuitry, resulting in more chip area and power being used up; and
large resistors R
21
and R
22
must be used in order to limit power consumption by the generator circuit
2
, resulting in further expenditure of chip area.
A further prior approach is based on the observation that many analog integrated circuits, especially those provided with converters, include differential circuits adapted to provide two voltage values whose difference &Dgr;V is stable with respect to temperature. A circuit that provides a temperature-stable voltage that is a different value from the silicon layer band-gap value, based on the voltage difference &Dgr;V, is shown generally and schematically at
3
in FIG.
3
.
This circuit
3
comprises essentially an operational amplifier OA
3
, having an inverting (−) input terminal connected to a first input terminal IN
31
of the circuit
3
through a first resistive element R
31
, and having a non-inverting (+) input terminal connected to a second input terminal IN
32
of the circuit
3
.
In particular, a voltage difference &Dgr;V is established between the input terminals IN
31
and IN
32
, which is stable with respect to temperature.
The operational amplifier OA
3
also has an output terminal connected to the respective control terminals of first and second MOS transistors M
31
and M
32
.
The first transistor M
31
is connected between the inverting (−) input terminal of the operational amplifier OA
3
and a ground reference GND, while the second transistor M
32
is connected between a current-mirror circuit CM and ground GND.
This current-mirror circuit
Nicollini Germano
Pernici Sergio
Stevenazzi Fabio
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