Circuit for zero-run developing RUN/LEVEL sets and method for ze

Details Circuit for zero-run developing RUN/LEVEL sets and method for ze Circuit for zero-run developing RUN/LEVEL sets and method for ze

1996-02-21

1998-04-07

Gaffin, Jeffrey A.

Coded data generation or conversion

Digital code to digital code converters

To or from bit count codes

341 50, H04N 1104

Patent

active

057369453

ABSTRACT:
A zero-run developing circuit for performing a zero-run developing process for placing zeros represented by a run between first non-zero data and second non-zero data of a block of a predetermined number of run-length signals, each of which is composed of the level of the value of non-zero data and the run that is the number of zero-data followed by the non-zero data is disclosed, that comprises a latch circuit for latching the levels of the predetermined number of the non-zero data, a first write position generating circuit for generating a first latch position of the latch circuit at which the first non-zero data is written corresponding to a first run length signal, and a second write position generating circuit for generating a second latch position of the latch circuit at which the second non-zero data is written corresponding to the first run-length signal and a second run-length signal.

REFERENCES:
patent: 5363097 (1994-11-01), Jan
patent: 5369045 (1994-11-01), Choi et al.
patent: 5369405 (1994-11-01), Choi et al.

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