Circuit for two PLLs for horizontal deflection

Details Circuit for two PLLs for horizontal deflection Circuit for two PLLs for horizontal deflection

2006-09-05

2006-09-05

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S156000

Reexamination Certificate

active

07102398

ABSTRACT:
A circuit for horizontal deflection includes a first PLL circuit that is arranged to provide a first PLL output signal, and a second PLL circuit that is arranged to provide a second PLL output signal. A first PLL circuit is arranged to provide equalizing pulse removal. The first PLL circuit includes a gated PFD and an equalization pulse removal logic circuit. The equalization pulse removal logic circuit is arranged such that, if equalizing pulses occur in a sync signal, the gated PFD is gated during each equalizing pulse. The second PLL circuit is arranged to provide a wide capture range, and to lock a center of a pulse of the center of the feedback signal with the leading edge of the first PLL output signal. The second PLL circuit includes a frequency comparator circuit, a PFD, and a phase detector. The frequency comparator circuit is arranged to select either the PFD or the phase detector.

REFERENCES:
patent: 5223931 (1993-06-01), Fernsler et al.
patent: 6483361 (2002-11-01), Chiu
patent: 6642747 (2003-11-01), Chiu
patent: 6795043 (2004-09-01), Shibata
National Semiconductor Corporation, “Video Sync Separator”, LMM1881, LM1881-X, Jun. 2003, pp. 1-12.

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