Circuit for transparent scan path testing of integrated circuit

Details Circuit for transparent scan path testing of integrated circuit Circuit for transparent scan path testing of integrated circuit

1988-09-22

1991-02-19

Eisenzopf, Reinhard J.

Excavating

G01R 1512, G01R 3128

Patent

active

049950398

ABSTRACT:
In a circuit for testing integrated circuit devices, scan registers (8.about.16) and data selecting circuits (20-28) are connected between a plurality of circuit blocks (29.about.31) in correspondence with the number of bits of the data, with the scan registers connected to each other by a shift register path so as to have a function of one shift register as a whole. A register selecting circuit (20.about.28) is connected to a clock input terminal (T1, T2) of the scan register. The scan registers other than those corresponding to the logic circuit block to be tested are selected by the register selecting circuit. Consequently, clocks for scanning scan registers other than those provided before and after the required circuit block are eliminated, enabling reduction of time required for scan test.

REFERENCES:
patent: 4580066 (1986-04-01), Berndt
patent: 4698588 (1987-10-01), Hwang et al.
patent: 4710931 (1987-12-01), Bellay et al.
patent: 4710933 (1987-12-01), Powell et al.
patent: 4764926 (1988-08-01), Knight et al.
patent: 4780666 (1989-10-01), Sakashita et al.
S. DasGupta, "An Enhancement to LSSD and Some Applications of LSSD in Reliability, Availability, and Serviceability", The Proceedings of the International Symposium on Fault Tolerant Computers, (1980): 32,34.

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