Excavating
Patent
1996-06-28
1998-09-15
Meky, Moustafa M.
Excavating
371 471, G06F 1502
Patent
active
058093419
ABSTRACT:
A data communication circuit of a computer system, includes transmitter and receiver circuits each having first and second data paths for respectively communicating synchronously and asynchronously formatted data on an alternatively selected basis, and a control circuit for controlling such communications. Included in the first data paths of the transmitter and receiver circuits are certain field check generating or error checking circuitry which are switchably coupled by their respective control circuits to their corresponding second data paths when synchronously formatted data is being asynchronously communicated through the second data paths. Included in the second data paths of the transmitter and receiver circuits are certain mapping logic to respectively accomodate the transmission and reception of Async-HDLC formatted data with transparency mapping.
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patent: 5268934 (1993-12-01), Sharma et al.
patent: 5379327 (1995-01-01), Sharma et al.
patent: 5640433 (1997-06-01), Szczebak, Jr. et al.
patent: 5699365 (1997-12-01), Klayman et al.
Nimishakvi Hanumanthrao V.
Sivamani Kameswaran
Meky Moustafa M.
Nguyen Frank D.
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