Television – Synchronization – Sync separation
Reexamination Certificate
1996-12-12
2001-04-03
Peng, John (Department: 2614)
Television
Synchronization
Sync separation
C348S531000, C348S533000, C348S536000, C348S542000
Reexamination Certificate
active
06211920
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to circuits for the treatment of line sync pulse signals used to display data on a screen. More particularly, the invention relates to a filter allowing the elimination of equalizing signals in a composite signal. An application to the field of monitors is described.
2. Discussion of the Related Art
To control the display of data on a monitor, and particularly to control the sweeping of an electron beam on a screen, synchronization signals are used. A frame is a collection of lines used to form an image on a screen of a monitor.
The synchronization signals are added to the useful signal, which represents the data to be displayed. Synchronization signals contain information allowing the determination of a start of a line (horizontal, or line sync) and the beginning of a frame (vertical, or frame sync). The synchronization signals are typically pulsed logic signals, largely defined by the polarity, frequency and duration of the pulses they contain. The polarity of the pulses may be positive or negative, according to which of the rising or falling edges are used. These signals are used by phase locked loops (PLLs).
FIGS. 1
a
and
1
b
illustrate such horizontal and vertical sync signals, H, V respectively. The signals represented are both of positive polarity and formed by pulses respectively labeled
101
and
102
. The line sync signals have a higher frequency, the frame sync pulses have a longer duration, and the active edges (rising—edges for positive polarity) of frame sync and line sync pulses are in phase.
Line and frame sync signals are either transmitted separately, or in the form of a single composite signal, which includes simultaneously the line and frame synchronization information.
FIG. 1
c
shows such a composite signal, C(H+V). This composite signal corresponds to the logical OR of the signals H in
FIG. 1
a
and V in
FIG. 1
b.
A drawback of this type of composite signal is the absence of edges during the frame sync pulse.
FIG. 1
d
shows a composite signal C including serration signals
103
which may be inserted into the composite signal to reduce this problem. The serration signals produce active edges in the composite signal during frame sync pulses. The active edges added by the serration signals typically have the same frequency and phase as the active edges of the line sync signal in the composite signal.
Finally,
FIG. 1
e
illustrates a composite signal C containing equalizing signals
104
. For essentially historic reasons related to television, such equalizing signals may be inserted into the composite signal between the line sync pulses before and after the frame sync pulses, and between the serration signals during the frame sync pulses. They double the frequency of active edges when present. Typically, equalizing pulses appear five line sync pulses before a frame sync pulse, and they disappear five line sync pulses after the end of the frame sync pulse.
The presence of equalizing signals in a composite signal may disturb the functioning of a PLL which uses the composite signal to control the line sweep. There is a risk of locking the PLL onto a frequency double that-of the line sync pulses.
FIG. 2
schematically illustrates a PLL circuit used in monitors, in particular with regard to the line sync signals. The line sync signals are mainly treated by a PLL labeled PLL-H. This PLL includes a comparator
10
, a charge pump
11
, a capacitive filter
12
, a voltage controlled oscillator (VCO)
13
, and a phase adjustment means
14
. The comparator
10
compares an input signal (line sync H or composite signal C) with a reference pulse signal Sref. According to the result of this comparison, the comparator controls charge pump
11
. This pump
11
charges or discharges filter
12
so that a voltage Vref at the terminal of the filter
12
represents the result of the comparison. Oscillator
13
produces a triangular signal Vosch, the frequency of which is proportional to the voltage Vref. Signal Vosch is later transformed into pulse signal Sref by means
14
. The position of edges in signal Sref is determined by a phase adjustment signal Sadj.
Comparator
10
is preferably a phase frequency comparator, which avoids locking PLL-H on a multiple of the line sync frequency. Once the input H/C and reference Sref sync signals are in phase and at the same frequency, voltage Vref stabilizes. A detection means
15
will generate a signal DETVER, the state of this signal indicating whether the PLL is in lock with the frequency and phase of the input signal.
Typically, an input interface
17
a
and an input/output interface
18
allow the input synchronization signals to be provided to PLL-H and to a frame sync signal treatment means
16
. The input interface is for example a polarity detecting and signal cleaning interface, which provides positive polarity signals for use internally.
The interface
17
a
is connected to interface
18
by a circuit
17
b,
which is for example an integrator with integrated capacitor.
If the horizontal and vertical synchronization signals are separate, interface
17
a
supplies line sync signals H to PLL-H, and interface
18
provides frame sync signals V to means
16
.
If the received signal is a composite signal, the input interface supplies the composite signal (rectified or not) to PLL-H and circuit
17
b.
FIG. 3
c
shows a frame sync signal TRAMEXT, produced by circuit
17
b,
by extraction from the signal received by interface
17
a,
if this signal is a composite signal. Frame sync signal TRAMEXT is delayed by an amount d.
Referring to
FIG. 3
b,
a classic technique for producing an extracted frame sync signal is to control the charging and discharging of the integrated capacitor of circuit
17
b
according to received pulses. Then, the voltage at the terminals of the integrated capacitor may be compared to a reference voltage, this reference voltage being chosen so as to not be reached when the charging period corresponds to the duration of a line sync pulse.
Circuit
17
b
typically includes an edge detector, such as a latch, to control a switching circuit included in interface
18
to supply signal TRAMEXT to means
16
and externally. Signal TRAMEXT may be used to inhibit PLL-H to avoid drifting of this PLL during reception of frame sync signals, if the sync signal is a composite signal.
The use of a phase/frequency comparator
10
may be preferable to the use of a simple phase detector, because locking PLL-H into a multiple frequency when only line sync pulses are present is then avoided. A problem is that this type of comparator is intolerant to an absence of pulses (for example, during a frame sync pulse without serration pulses) and to the presence of parasitic or unwanted pulses such as equalizing pulses.
SUMMARY OF THE INVENTION
An object of the invention is to provide a circuit avoiding the above mentioned problems. In order to achieve this, in one embodiment, a windowing operation is used, centered on the active edges of the received line sync pulses. In this way, drift which could be caused by equalizing pulses is eliminated.
An embodiment of the invention includes a circuit for the treatment of signals including line sync pulses used to display data on a screen, the circuit including a PLL to control the line sweep of the screen according to the active edges of the sync pulses. The circuit may also include means for producing a windowing filter to filter the signal received by the PLL when in an active state so that active edges of this received signal which are out of phase with active edges of the line sync pulses are eliminated.
In one embodiment, this windowing is combined with a windowing created by a frame sync signal treatment circuit, so that the windowing is effected around and during the frame synchronization pulses. This may avoid locking onto a multiple of the line sync frequency, which could happen with permanent windowing, in the case of an instantaneous frequency rise to a multiple of the previous frequency.
A per
Cirot Eric
Lebouleux Nicolas
Galanthay Theodore E.
Morris James H.
Natnael Paulos
Peng John
SGS-Thomson Microelectronics S.A.
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