Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – Lumped type parameters
Reexamination Certificate
2002-01-29
2004-08-10
Deb, Anjan (Department: 2858)
Electricity: measuring and testing
Impedance, admittance or other quantities representative of...
Lumped type parameters
C235S492000
Reexamination Certificate
active
06774663
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to detection circuits, and more particularly, to a detection circuit for detecting a defective power supply connection.
BACKGROUND OF THE INVENTION
Using a smart card as an example, the integrated circuit within such a card receives its power from a coupler or card reader, which typically includes Vdd and Gnd. The quality of this card/coupler link may be defective, wherein the serial contact resistance values are very high. The quality may be affected by wear and tear or corrosion of the pads of the integrated circuit. Another cause of deterioration in the quality of the card/coupler link is fraud. That is, an ill-intentioned third party may deliberately damage this link, for example, by putting adhesive on one or more pads of the card to cause it to operate abnormally.
When the card/coupler connection is defective with respect to the power supply pads, the internal power supply of the integrated circuit can be obtained indirectly by the input/output pads of the integrated circuit. This is done through the pull-down or pull-up elements (e.g., resistors and diodes) connected between these pads and an internal supply voltage. However, this may lead to a significant malfunctioning in the integrated circuit.
Taking as an example an integrated circuit with two power supply pads for receiving a ground voltage Gnd and a logic supply voltage Vdd through the coupler, at least one input/output pad with a ground (GND) pull-down element using a resistor will be referenced Rpd. This pad receives a default level from the coupler, which corresponds to ground. This level may change during very short periods of time corresponding to clock pulses of the circuit/coupler link.
By default, the integrated circuit is in a first mode of operation in which it consumes current I
1
(for example, in a memory read mode). Upon a command from the coupler, it may pass into a second mode of operation in which it consumes higher current I
2
(for example, in a memory write mode).
An integrated circuit of this type usually comprises a power-on reset device depending on the potential difference between the internal levels of the logic supply voltage and ground in the integrated circuit. This device is active when the circuit is powered on and off. In particular, this device is activated whenever the potential difference between the internal levels of the logic supply voltage and ground falls below a specified threshold. This threshold shall be referenced Vpor. It is assumed in the example that the threshold Vpor is set at 4 volts for a five-volt logic power supply voltage Vdd.
Assuming that the power supply pad associated with ground GND shows a very high series contact resistance, ground Gnd is not properly transmitted within the integrated circuit by the pad. The input/output pad which is grounded brings the internal ground line to a voltage level VA by the associated pull-down device.
If the integrated circuit is in the first mode of operation, this internal ground level VA obtained by the pull-down resistor Rpd is equal to Rpd*I
1
. This means that the integrated circuit could operate properly in this first mode of operation provided that the internal ground level V
1
is such that the ground potential difference between the internal level Vddint of the logic supply voltage Vdd and this internal level of ground remains higher than the reset threshold Vpor. This is written as follows:
Vddint−Va>Vpor; that is
Vddint−Rpd*I
1
>Vpor.
If the integrated circuit goes into the second mode of operation, the internal level Va of ground goes to a higher level (I
2
>I
1
) equal to Rpd*I
2
. It is then possible to have a situation where the potential difference between the internal levels of the logic supply voltage Vdd and ground Gnd fall below the reset threshold Vpor of the integrated circuit. This will deactivate the integrated circuit. Since this change in situation is not immediate, it may happen that a portion of the command related to the second mode of operation (writing in memory) is executed. This is even more disadvantageous.
SUMMARY OF THE INVENTION
In view of the foregoing invention, an object of the invention to detect a defective connection of an integrated circuit with a power supply.
Another object of the invention is to detect high values of series contact resistances at the power supply pads of an integrated circuit.
Yet another object of the invention is to detect when the power supply for an integrated circuit is not obtained by the input/output pad pull-down or pull-up devices of the integrated circuit.
These and other objects, advantages and features of the invention are provided by at least one voltage level comparison device that compares voltage levels between an internal power supply line of the integrated circuit and an input/output pad of the integrated circuit. The integrated circuit comprises a pull-down or pull-up device connected between the input/output pad and the internal power supply line.
If the voltage level at the internal supply line is dictated by the pull-down or pull-up device, this level may be greater than or lower than the voltage level of the pad. Depending on whether this difference is above or below a predetermined detection threshold, the supply is determined to be a good connection or a bad connection. Should the supply be detected as being a bad connection, the integrated circuit will inhibit its own operation. The detection device according to the invention then acts as a safety device, preventing any malfunctioning in the integrated circuit that might be caused by a defective power supply connection.
The detection device according to the invention preferably comprises a comparison circuit associated with each internal supply level. If, for a given supply voltage level, there are several input/output pads, with a pull-down or pull-up device at this voltage level, then a comparison device is preferably provided for each of these pads. A detection device according to the invention is especially recommended for actively combating attempts at fraud designed to give rise to the abnormal operation of the integrated circuit.
The device can also be applied in cases of normal use of the integrated circuit to detect wear and tear or corrosion of the supply pads. In this type of application, the detection device will preferably be used in combination with protection circuits that may exist at the input/output pads themselves. These input/output pads may themselves be worn out or corroded due to the normal use of the integrated circuit. Hence, the power level transmitted by these pads may be degraded and the output results of the detection device according to the invention must then be considered in combination with other safety information.
As claimed, the invention therefore relates to a device for the detection of a defective power supply connection in an integrated circuit. According to the invention, in an integrated circuit comprising at least one power supply pad for applying an external power supply to an internal power supply line of the integrated circuit and at least one input/output pad with which there is associated a pull-down or pull-up device connected between the pad and the internal supply line, the detection device comprises a circuit for the comparison of the voltage levels between the pad and the internal supply line. The signal delivered by the detection device may be used to inhibit the internal operation of the integrated circuit.
REFERENCES:
patent: 6027029 (2000-02-01), Kim
Patent Abstracts of Japan, vol. 013, No. 570, (P-977), Dec. 18, 1989 & JP 01237894 A (Hitachi Maxell Ltd.), Sep. 22, 1989.
Patent Abstracts of Japan, vol. 1995, No. 02, Mar. 31, 1995 & JP 06325222 A (Fuji Electric Co. Ltd.) Nov. 25, 1994.
Patent Abstracts of Japan, vol. 2000, No. 16, May 8, 2001 & JP 2001 005916 A (Matsushita Electric Ind. Co. Ltd.) Jan. 12, 2001.
Kari Ahmed
Moreaux Christophe
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Deb Anjan
Jorgenson Lisa K.
Lair Donald M
STMicroelectronics SA
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