Circuit for the buffer storage of a bit, and use of the circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit

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Details

327200, 327211, 327219, 327415, H03K 3356

Patent

active

054481945

ABSTRACT:
A storage element is provided in a circuit arrangement for latching one bit. A first MOS transistor (T1) is provided which, when a first control signal (S1) is present, switches an input signal corresponding to the bit to the input of the storage element. The storage element is provided with circuit elements by which an output signal at the output of the storage element is brought to a predetermined potential in dependence on the level of the input signal. The circuit arrangement is particularly suitable for constructing an address latch for DRAMs, particularly of the 16-M generation.

REFERENCES:
patent: 4156940 (1979-05-01), Hollingsworth et al.
patent: 4754165 (1988-06-01), Cornish
patent: 5003513 (1991-03-01), Porter et al.
patent: 5073873 (1991-12-01), Nogami
patent: 5204560 (1993-04-01), Bredin et al.
patent: 5347173 (1994-09-01), McAdams
patent: 5349243 (1994-09-01), McClure
patent: 5396108 (1995-03-01), McClure
"Row Address Buffer and Decoder Circuits for CMOS Dynamic RAM", IBM Technical Disclosure Bulletin, vol. 28, No. 1, Jun. 1985, pp. 421-425.

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