Excavating
Patent
1988-09-22
1990-11-27
Smith, Jerry
Excavating
371 226, 371 251, G01R 3128
Patent
active
049742264
ABSTRACT:
Test data stored in a data register 13a are applied to a data generator 11a and compared with a 1 bit signal stored in a scan latch 1c to determine the coincidence or non-coincidence therebetween. Outputs from the data generator 11a are applied to RAM 10 to be written in a designated region in a memory cell array 6. Data read from the said region of the memory cell array 6 are compared with expected value data in a comparator 12. Thus, the collation of data is carried out.
REFERENCES:
patent: 4534028 (1985-08-01), Trischler
patent: 4775977 (1988-10-01), Dehara
patent: 4827476 (1989-05-01), Garcia
"Gate Level Self-Test for Field-Replaceable Unit", IBM Technical Disclosure Bulletin, vol. 28, No. 11, pp. 4766-4767 (Apr. 1986).
"ROS combined with LSSD SRL Circuit for Fast Logic Testing", IBM Technical Disclosure Bulletin, vol. 30, No. 2, pp. 944-945 (Jul. 1988).
"Built-in Self Testing of Embedded Memories" by Sunil K. Jain and Charles E. Stroud, IEEE TEST AND DESIGN, pp. 27-37 (Oct. 1986).
T. Chan et al "Advanced Structured Arrays Combine High Density Memories with Channel-Free Logic Array" IEEE 1987 Custom Integrated Circuits Conference (Jul. 1987): 39, 43.
E. Eichelberger and T. Williams, "A Logic Design Structure for LSI Testability" The Proceedings of the 14th Design Automation Conference, 1977, IEEE (Reprint): 462, 468.
Fujimori Kumiko
Shinohara Hirofumi
Beausoliel Robert W.
Mitsubishi Denki & Kabushiki Kaisha
Smith Jerry
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