Circuit for testing an integrated circuit

Details Circuit for testing an integrated circuit Circuit for testing an integrated circuit

2002-07-30

2004-08-24

Cuneo, Kamand (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB

Reexamination Certificate

active

06781398

ABSTRACT:

FIELD OF INVENTION
The invention relates to a circuit apparatus for testing at least one test signal output by an integrated circuit.
RELATED APPLICATIONS
This application claims the benefit of the Jul. 31, 2001 filing date of German application 101 37 345.7-53, the contents of which are herein incorporated by reference.
BACKGROUND
Integrated circuits undergo a multiplicity of different test methods during and after their fabrication process. With the continually growing complexity of modern integrated circuits—in particular DRAM memories—the required test methods also become more complex and require ever more powerful test systems. Since the typical product lifetime, in particular of modern memory components, often amounts to only a few months, it is impracticable for cost reasons to individually create anew a test system suitable for a specific memory component. Therefore, modern test systems for the functional testing of complex integrated circuits are usually individually programmable within wide limits, in order to be able to be adapted to ever new DUTs (device under test). Therefore, the test systems used in the semiconductor memory industry, some of which have procurement prices of in excess of one million Euros, can typically be used over a plurality of product generations.
A critical bottleneck of commercial test systems for integrated circuits, for example of the Advantest T 5581 test system for DRAM-DIMMS, is the number of freely programmable and fast input/output terminals (I/O pins). By way of example, the Advantest T 5581 D-type test system, for parallel test purposes, has over n*72 fast, freely programmable I/O pins (n=4, 8 or 16) which suffice for complete functional testing of an SDR-DIMM (single data rate DIMM) with high parallelism and flexibility (in particular owing to the scrambling of the PCB (printed circuit board) that is to be taken into account). DDR-DIMMs (double data rate DIMMs), which are increasingly being used, have a further 18 terminals, however, on account of the DQS signals (data query strobe) arising in this case, so that flexible and highly parallel functional testing of, in particular, the DQS signals during the read operation is problematic with this test system.
Therefore, performance boards (base boards or HiFix boards) have conventionally had to be used, on which DDR-DIMMs have been able to be tested only 4-fold in parallel with low flexibility.
SUMMARY
In view of the above disadvantages, it is an object of the invention, therefore, to extend in particular conventional test systems, whose number of freely programmable fast I/O pins (i.e. the number of comparators) does not suffice for a flexible and complete functional test of an integrated circuit, in a simple and cost-effective manner for the new test task.
According to the invention, a circuit apparatus for testing at least one test signal output by an integrated circuit comprises
at least one test signal input for the signal inputting of the test signal;
at least one reference signal input for the signal inputting of a reference signal;
at least one comparator device, which is designed for a signal comparison of the test signal with the reference signal and for outputting an error signal if the signal comparison yields an error;
at least one error memory device for storing the error signal; and
at least one error signal output connected to the error memory device.
According to the invention, a circuit apparatus is used which has inputs for the signal to be tested (e.g. the DQS signal of DDR-DIMM) and for a reference signal chosen in accordance with the corresponding specification. The test signal is input into the test signal input from the integrated circuit to be tested.
The reference signal can be output by an external test system. It is advantageous that there is no need to use a “valuable” fast I/O pin of the test system in order to output the reference signal to the circuit apparatus. Instead of this, a so-called driver output of the test system may preferably be used, which driver output, although designed for fast and freely programmable signal outputting, is not designed for signal inputting. Although it is often the case in test systems which are used for highly complex test tasks that all the fast I/O pins which can compare signals output by the integrated circuit to be tested with reference signals are occupied, so that additional signals of the integrated circuit cannot be directly tested at the same time, such test systems nonetheless typically also have a multiplicity of additional driver outputs which are not yet occupied.
The circuit apparatus according to the invention enables these hitherto unutilized driver outputs of the test system to be preferably used to test the additional (test) signals of the integrated circuit to be tested. The test signal is compared with the reference signal (from the driver output of the test system) in the comparator device of the circuit apparatus. If the signal comparison turns out to be negative, i.e. the test signal does not satisfy the test reference prescribed by the reference signal, the comparator device generates an error signal which is stored in an error memory device. The error memory device can be read externally via the error signal output in particular by the external test system.
Although a signal input of the test system is required for the read-out operation of the error memory device, this test result input of the test system need not be a “fast” signal input, since the error state stored in the error memory device can also be read out with a read-out rate which is significantly lower than the signal rate of the test and reference signals. Such “slow” programmable signal inputs of the test system are often still available even when all the “fast” inputs are already occupied.
Consequently, the circuit device enables the functional testing of an additional signal output of the integrated circuit (i.e. of the test signal) without this requiring an additional fast I/O pin of the test system. Instead of this, the circuit apparatus according to the invention makes it possible to use a fast driver output and also a slow signal input of the test system.
It is particularly advantageous, moreover, that a single driver output of the test system can be connected to a multiplicity of reference signal inputs of the circuit apparatuses in order to test a multiplicity of DQS signals of a DDR-DIMM. In this case, a multiplicity of test signal inputs and comparator devices are correspondingly provided. The error evaluation can in this case be effected separately for each test signal (i.e. DQS-fine error testing) if each comparator device is assigned an error memory device. It is often sufficient, however, for the error evaluation merely to be of DUT-fine design, so that, in particular, a single error memory device per DUT may be sufficient.
Preferably, the comparator device is designed for a voltage comparison of the test signal with the reference signal and for outputting a binary error signal. The voltage comparison may be performed by the comparator device in particular continuously or only when said comparator device is in a comparison mode which can be activated externally. It is advantageous to provide a binary signal as the error signal. In this case, the test result input of the test system, which input is connected to the error signal output of the circuit apparatus, need be, for example, only a simple (slow) TTL input.
Preferably, the error memory device comprises at least one flip-flop circuit. Preferably, the error memory device is connected to a reset signal input for erasing an error state of the error memory device. The reset signal can be generated by a programmable signal output of the test system, which output may be, in particular, slow and binary.
Preferably, the test signal input is connected to at least one first and one second comparator device and at least one first and one second reference signal input are provided, wherein
the first comparator device is designed for outputting a first error signal i

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