Circuit for testing a semiconductor chip having embedded arrays

Details Circuit for testing a semiconductor chip having embedded arrays Circuit for testing a semiconductor chip having embedded arrays

1995-02-21

1998-02-10

Beausoliel, Jr., Robert W.

Excavating

365201, G01R 3128

Patent

active

057176965

ABSTRACT:
A test circuit applicable to chips having embedded arrays intermixed with logic is described. Depending on a control signal, the test circuit connects or isolates the arrays to and from the logic. The test circuit operates as a switch placed between the power supply rail of the logic and the power supply rail of the arrays. All input gates are cross-connected to the power supply rail of the logic, and each output gate is connected to the corresponding power supply rail of the arrays. During TEST mode, the control signal turns off the test circuit, cutting off the arrays. The logic is tested while the memory cells remain unselected. Faulty chips are rejected. When the value of the control signal is inverted, a control gate connects all the power supply rails of the arrays to the power supply rail of the logic. The test sequence for the embedded array is then applied. Faulty memory cells are replaced with repairable ones; otherwise, the faulty chips are rejected. Thus, the manufacturing yield of the mixed chips is improved.

REFERENCES:
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patent: 5285119 (1994-02-01), Takahashi
patent: 5294883 (1994-03-01), Akiki et al.
patent: 5355331 (1994-10-01), Takase et al.
patent: 5444391 (1995-08-01), Moitie et al.
patent: 5491665 (1996-02-01), Sachdev
patent: 5497117 (1996-03-01), Nakajima et al.
patent: 5523977 (1996-06-01), Tobita et al.

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