Circuit for testability

Details Circuit for testability Circuit for testability

1990-02-01

1992-11-03

Smith, Jerry

Excavating

371 225, H04B 1700

Patent

active

051611600

ABSTRACT:
An evaluation facilitating circuit incorporated in a logic circuit having a plurality of functional blocks, includes: many scan register groups obtained by dividing many F/Fs provided in each functional block, many scan paths for scanning a plurality of test data used for input and output operations for the scan register groups, wherein a scan path is provided for each scan register group, and a decoder for designating the scan paths and controlling the input and output operations of test signals used for testing the scan register groups. A first scan register group in each functional group is composed of scan registers only used for the input operations to other functional blocks, a second scan register group is composed of scan registers only used for the output operations to other functional blocks and a third scan register group is composed of scan registers used for the input and output operations to the same functional block. Each scan path is connected to a common bus provided in the functional circuit. The common bus includes many signal lines through which the test data is transferred, and the scan path connected to a first scan register group is connected to a first pair of signal lines, the scan path connected to the second scan register group is connected to a second pair of signal lines, and the scan path connected to the third scan register group is connected to a third pair of signal lines.

REFERENCES:
patent: 4697267 (1987-09-01), Wakai
patent: 4698588 (1987-10-01), Hwang et al.
patent: 4710931 (1987-12-01), Bellay et al.
patent: 4766593 (1988-08-01), Cates
patent: 4799004 (1989-01-01), Mori
patent: 4912395 (1990-03-01), Sato et al.
patent: 4974226 (1990-11-01), Fujimori et al.
patent: 4995039 (1991-02-01), Sakashita et al.

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