Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-12-26
2001-12-18
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S200000, C365S185180
Reexamination Certificate
active
06331949
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device having a redundant function of relieving a defective portion inside a memory cell array by substituting a reserved or relief portion (redundancy) for the defective portion, and in particular, to a circuit incorporated in such a nonvolatile semiconductor memory device for storing and latching the address data of the defective portion.
In connection with nonvolatile semiconductor memory devices, there is a known method for replacing defective bit lines, defective word lines and defective memory cells with reserved normal ones (redundancy) to increase the yield. In the nonvolatile semiconductor memory device utilizing such a method, the addresses of the defective bit lines, the defective word lines and the defective memory cells, i.e., the defective address data are required to be stored.
(First Related Background Art)
To store the data representing the defective address, use of electrically rewritable nonvolatile semiconductor memory cells is known from Japanese Patent Application Laid-Open No. 5-276018. An example of such a method is described below with reference to
FIG. 25
showing a circuit for storing and latching the defective address data. For example, the case in which an address “101” is stored in this circuit is described below. The circuit shown in
FIG. 25
is adapted to a flash memory, represented by ETOX™, to which writing is executed by using a channel hot electron. In the conventional flash memory of this type, memory cells M
0
, M
1
, and M
2
in an initial state have a threshold (gate threshold voltage) of about 0.5 volts to 2.5 volts.
The writing or programming is executed by using channel hot electrons as follows. Initially, an H(high)-level equivalent to a value of “1” is supplied to a data line DL shown in FIG.
25
. Then, an L(low)-level is latched in a write data latch circuit DLC. On the other hand, the potential of a word line WL for the memory cells M
0
, M
1
, and M
2
rises to a Vpp (for example, 10 volts), and the potential of a bit line selection signal bitsel
0
has also the potential Vpp. At this time, 0 volts is output from a level shifter HV, with a bit line BL
0
having a floating state and the threshold of the memory cell M
0
kept at the low voltage (2.5 volts or less). Then in writing data “0”, an L-level is supplied to the data line DL, an H-level is latched in the write data latch circuit DLC, and the potential of the word line WL of the memory cells rises to the Vpp level. The potential of the bit line selection signal bitsell also becomes the Vpp level. The output of the level shifter HV, in which the H-level is latched, assumes the potential Vpp. Thus, a voltage hhprg (for example, 6 volts) is output to a bit line BL
1
. As a result, the threshold of the memory cell M
1
rises to a voltage of 5 volts or more owing to the channel hot electrons, as shown in FIG.
20
. The memory cell M
2
is kept in a low-threshold state, similar to the memory cell M
0
.
The operation of the defective address latch circuit ALC (ALC
0
, ALC
1
, ALC
2
) upon turn-on of the power supply of the memory device will be described below with reference to
FIGS. 21A
,
21
B,
22
A, and
22
B.
FIGS. 21A and 21B
each show a circuitry of a basic cell for storing one bit of the defective address data. First, when the data “0” is stored in the memory cell M
1
, as shown in
FIG. 21B
, as a supply voltage Vcc rises, the potential of a node A increases owing to coupling, following the supply voltage Vcc, as indicated by a power supply turn-on waveform of FIG.
22
B. Because the threshold, Vth, of the memory cell M
1
is 5 volts or more in this case, the memory cell M
1
is off and electric current does not flow therethrough, and an output radd
1
latches and supplies a “0”.
Referring to
FIG. 21A
, the memory cells M
0
and M
2
store the data “1”. Thus, as indicated by a power supply turn-on waveform of
FIG. 22A
, once the word line has a voltage of 2.5 volts or more, electric current starts to flow through the memory cells M
0
and M
2
, and the node A, which initially followed the supply voltage Vcc, drops to the level L. This is because electric current flows through the memory cells M
0
and M
2
. As a result, outputs radd
0
and radd
2
have a “1”-latched state, respectively.
(Second Related Background Art)
In the first related background art, one bit of address information is stored by one memory cell. Another method for storing address information is known from Japanese Patent Application Laid-Open No. 8-22699, in which two memory cells are used to store one bit of address information. An example of such a method is described below with reference to
FIG. 26
on the case in which an address “101” is stored in the circuit of FIG.
26
. The circuit shown in
FIG. 26
is applied to a flash memory (represented by ETOX™) to which programming is executed using a channel hot electron. In the known flash memory of this type, thresholds of memory cells are about 0.5 volts-2.5 volts in an initial state.
FIG. 20
shows the threshold states.
According to this technique, programming is executed by using the channel hot electron as follows. Initially, an H(high)-level is supplied to a data line DL shown in FIG.
26
. Then, an L(low)-level is latched into a write data latch circuit DLC. The potential of a word line WL associated with the memory cells M
0
through M
5
rises to a Vpp (for example, 10 volts), and the potential of a bit line selection signal bitsel
0
has also the potential Vpp. At this time, a bit line BL
0
is in a floating state. As a result, the threshold of the memory cell M
0
is kept at the low level (2.5 volts or less).
In the following operation, an L-level is supplied to the data line DL, and an H-level is latched into the write data latch circuit DLC. On the other hand, the potential of the word line WL for the memory cells M
0
through M
5
rises to Vpp (for example, 10 volts) . In addition, the potential of the bit line selection signal bitsell becomes Vpp and a voltage hhprg (for example, 6 volts) is supplied to a bit line BL
1
. Channel hot electrons are thus generated in the memory cell M
1
and its threshold rises to a voltage of 5 volts or more.
On the other hand, to have a second defective address latch circuit ALC
1
latch a “0”, the memory cell M
2
is placed in a programmed state (the threshold being 5 volts or more), and the memory cell M
3
is kept in the erased state (in which the threshold is low). Also, to have a third defective address latch circuit ALC
1
latch data “1”, the memory cell M
4
is placed in the erased state, while the memory cell M
5
is kept in the programmed state.
The defective address latch circuits ALC
0
, ALC
1
, and ALC
2
each latch one data by using two memory cells having different threshold states. More specifically, one data is latched using one memory cell whose threshold is 2.5 volts or less in combination with the other memory cell whose threshold is 5 volts or more.
The address latch operation will be described below with reference to
FIGS. 23A
,
23
B,
24
A, and
24
B.
First, latch of data “0” by the defective address latch circuit is described below with reference to
FIGS. 23A and 24A
. In this case, the threshold, Vth, of the memory cell M
0
is high (Vth≧5 volts), whereas the threshold, Vth, of the memory cell M
1
is low (Vth≦2.5 volts). As indicated by a power supply turn-on waveform of
FIG. 24A
, when the supply voltage Vcc increases and the potential of the word line WL becomes 2.5 volts or more, an electric charge is extracted from the node A because the threshold of the memory cell M
1
is low. Thus, the potential of the node A becomes 0 volts. At this time, because the threshold of the memory cell M
0
is 5 volts or more, the potential of the node B is kept at a high level (2.5 volts) . As a result, the ground-side potential Vss (data “0”) is supplied to the output radd.
Next, latch of data “1” by the defective address latch circuit is described below with reference to
FIGS. 23
Hoang Huan
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
LandOfFree
Circuit for storing and latching defective address data for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit for storing and latching defective address data for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for storing and latching defective address data for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2593017