Circuit for standby current reduction

Details Circuit for standby current reduction Circuit for standby current reduction

1999-02-03

2001-09-11

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S210000, C327S211000, C326S095000

Reexamination Certificate

active

06288586

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a circuit for reducing a standby current occurred in a low voltage circuit.
2. Discussion of the Related Art
In general, a transistor voltage is lowered for reducing a signal transmission speed in the low voltage circuit, causing significant increase of a threshold leakage current during the standby, of which reduction becomes a key problem.
A background art circuit for reducing a standby current will be explained with reference to the attached drawings. In the background art circuit for reducing a standby current, for reducing leakage currents flowing through a plurality of logic circuit units, PMOS transistors and NMOS transistors, both with high threshold voltages are provided external to the logic circuit units for controlling the leakage currents flowing through an entire circuit.
FIG. 1
illustrates a first exemplary background art circuit for reducing a standby current.
Referring to
FIG. 1
, the first exemplary background art circuit for reducing a standby current is provided with a main power supply line Vcc and a ground line Vss, a sub-power supply line Vcc-L and a sub-ground line Vss-L, a PMOS transistor HPM
1
between the main power supply line and the sub-power supply line, an NMOS transistor HNM
1
between the main ground line and the sub-ground line, and a plurality of logic circuits
11
between the sub-power supply line and the sub-ground line. Each of the logic circuits
11
is provided with a plurality of PMOS transistors and NMOS transistors, both of low threshold voltages. The PMOS transistor HPM
1
between the main power supply line and the sub-power supply line and the NMOS transistor HNM
1
between the main ground line and the sub-ground line have threshold voltages relatively higher than the transistors in the logic circuits
11
. The NMOS transistor HNM
1
has a gate adapted to be applied of an active signal ACT, and the PMOS transistor HPM
1
has a gate adapted to be applied of an active bar signal {overscore (ACT)}.
The operation of the first exemplary background art circuit for reducing a standby current will be explained.
As shown in
FIG. 1
, when the circuit is active, the PMOS transistor HPM
1
and the NMOS transistor HNM
1
are turned on, to charge the sub-power supply line Vcc-L to a voltage of Vcc level and the sub-ground line Vss-L to a voltage of Vss level. Accordingly, the circuit is operative as a general circuit in which an output is provided according to a system of the logic circuit
11
. When the circuit is standby, the PMOS transistor HPM
1
and the NMOS transistor HNM
1
are turned off, causing the sub-power supply line and the sub-ground line separated from the main power supply line and the main ground line respectively, to make a voltage on the sub-power supply line to become a power supply voltage applied to the plurality of logic circuit
11
and a voltage on the sub-ground line to become a ground voltage applied on the logic circuit
11
. In this instance, the leakage current flowing through the logic circuit is increased as the power supply voltage is the higher, and vice versa. By separating the sub-power supply line and the sub-ground line from the main power supply line and the main ground line respectively, the power supply voltage to the logic circuit
11
can be lower, leading to a reduction of the leakage current using such a characteristic.
FIG. 2
illustrates a second exemplary background art circuit for reducing a standby current.
Referring to
FIG. 2
, the second exemplary background art circuit for reducing a standby current is provided with a main power supply line Vcc, a main ground line Vss, a sub-power supply line Vcc-L, a sub-ground line Vss-L, a PMOS transistor HPM
1
between the main power supply line and the sub-power supply line, an NMOS transistor HNM
1
between the main ground line and the sub-ground line, a first logic circuit
21
between the main-power supply line and the sub-ground line and a second logic circuit
21
a
between the sub-power supply line and the main ground line. There may be a plurality of logic circuits other than the first, and second logic circuits
21
and
21
a
depending on a circuit system. The first, and second logic circuits
21
and
21
a
are provided with a plurality of PMOS transistors and a plurality of NMOS transistors, wherein logic circuits having transistors turned on predicting standby states in advance are connected to the main power supply line and the sub-ground line and logic circuits having transistors turned off predicting standby states in advance are connected to the sub-power supply line and the main-ground line, thereby reducing loads on the sub-power supply line and sub-ground line to half when the two logic circuits
21
and
21
a
are operative.
However, the background art circuits for reducing a standby current have the following problems.
First, the optimization of sizes of transistors connecting main power supply line and sub-power supply line and main ground line and the sub-ground line for adjusting a time period required for returning from a standby state to an active state requires a long time.
Second, application of the circuit to a circuit automatic composition is difficult, in which the circuit is designed in a top-down fashion utilizing a netlist in which circuit design formats are provided as texts.
Third, the circuit requires much area and is complicated.
Fourth, the transistors of high threshold voltages provided between main power supply line and sub-power supply line and main ground line and the sub-ground line act like capacitors at returning from a standby state to an active state, causing the sub-power supply line and the sub-ground line to require much time periods in restoring to voltages identical to the voltages on the main power supply line and main ground line.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed a circuit for reducing a standby circuit that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a circuit for reducing a standby current which can minimize a leakage current, shorten a time period returning from a standby state back to an active state to a maximum, and allow automatic composition of the circuit, to overcome a limit of a current technology.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the circuit for reducing a standby current includes a PMOS transistor connected to a power supply voltage terminal, an NMOS transistor connected to a ground voltage terminal, and a switching device between the PMOS transistor and the NMOS transistor for cutting off a leakage current flowing to the NMOS transistor through the PMOS transistor.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4486673 (1984-12-01), Koike
patent: 4734597 (1988-03-01), Ullrich et al.
patent: 5245209 (1993-09-01), Ishigaki
patent: 5304833 (1994-04-01), Shigeki et al.
patent: 5329175 (1994-07-01), Peterson
patent: 5592114 (1997-01-01), Wu et al.
patent: 5642061 (1997-06-01), Gorny
patent: 5781052 (1998-06-01), Kleine
patent: 5917355 (1999-06-01), Klass

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