Circuit for stable synchronization of asynchronous data

Details Circuit for stable synchronization of asynchronous data Circuit for stable synchronization of asynchronous data

1988-11-07

1990-05-22

Safourek, Benedict V.

Pulse or digital communications

Spread spectrum

Direct sequence

341 61, H04L 702

Patent

active

049282905

ABSTRACT:
A circuit for the stable synchronization of an asynchronous data signal. The circuit comprises a first latch for receiving a first asynchronous data signal, a first delayed system clock signal, and a synchronized reset signal and for providing a system clock synchronized version of the first asynchronous data signal. A first delaying circuit receives a system clock signal and the first asynchronous data signal and provides the first delayed system clock signal. The circuit also includes a second latch for receiving a second asynchronous data signal which is a function of the inverse of the first asynchronous data signal and a second delayed system clock signal, and for providing the synchronized reset signal. A second delaying circuit receives the system clock signal and the first asynchronous data signal and provide the second delayed system clock signal.

REFERENCES:
patent: 3575215 (1971-04-01), Boddy
patent: 3612906 (1971-10-01), Kennedy
patent: 3751683 (1973-08-01), Drost
patent: 3961138 (1976-06-01), Fellinger
patent: 4007421 (1977-02-01), Lien
patent: 4229815 (1980-10-01), Cummiskey
patent: 4408333 (1983-10-01), Fujii
patent: 4498176 (1985-02-01), Wagner
patent: 4506165 (1985-03-01), Gulati et al.
patent: 4575644 (1986-03-01), Leslie
patent: 4629909 (1986-12-01), Cameron
Delay-Free Asynchronous Circuits with Constrained Line Delays, IEEE Transactions on Computers, Feb. 1969.

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