Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2002-09-24
2004-09-14
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S108000, C326S080000, C326S081000
Reexamination Certificate
active
06791392
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to signal level shift circuits that shift signal levels between different electric circuit systems operating based on different supply voltages, so that signals of one circuit system are converted to be suitable for another circuit system.
2. Description of the Related Art
FIG. 4A
shows a typical example of the configuration of a signal level shift circuit, which receives an input signal ‘IN’ whose level is 3V to provide an output signal ‘OUT’ whose level is 5V. That is, the overall configuration of
FIG. 4A
contains a VDDL circuit system operating based on a relatively low supply voltage VDDL of 3V, and a VDDH circuit system operating based on a relatively high supply voltage VDDH of 5V. The VDDL circuit system comprises inverters IV
1
and IV
2
for producing complementary signals with respect to the input signal IN. The VDDH circuit system comprises a level shift circuit LS, which forms a main part of the signal level shift circuit, and an inverter IV
3
for waveform shaping.
Specifically, the VDDL circuit system has a CMOS (i.e., Complementary Metal-Oxide Semiconductor) configuration consisting of the inverters IV
1
and IV
2
, which operate based on the supply voltage VDDL of 3V. Herein, the inverter IV
1
is supplied with the input signal IN from an external device (not shown), and the output terminal thereof is connected to the input terminal of the inverter IV
2
. That is, the inverter IV
1
outputs an inverse phase signal (or inversion signal) of the input signal IN, while the inverter IV
2
outputs a same phase signal of the input signal IN.
The level shift circuit LS comprises a load circuit portion consisting of p-channel metal-oxide field-effect transistors (hereinafter, referred to as PMOS transistors) TP
1
and TP
2
, and a drive circuit portion consisting of n-channel metal-oxide semiconductor field-effect transistors (hereinafter, referred to as NMOS transistors) TN
1
and TN
2
, wherein the load circuit portion is driven by the drive circuit portion. The sources of the PMOS transistors TP
1
and TP
2
are commonly connected with the voltage supply VDDH of 5V. In addition, the gates and drains of the PMOS transistors TP
1
and TP
2
are alternately connected to each other. That is, the gate of the PMOS transistor TP
1
is connected with the drain of the PMOS transistor TP
2
, and the gate of the PMOS transistor TP
2
is connected with the drain of the PMOS transistor TP
1
.
The drain of the NMOS transistor TN
1
is connected to the drain of the PMOS transistor TP
1
via a node Na, and the drain of the NMOS transistor TN
2
is connected to the drain of the PMOS transistor TP
2
via a node Nb. In addition, the sources of the NMOS transistors TN
1
and TN
2
are both grounded. The gate of the NMOS transistor TN
1
is supplied with the inverse phase signal of the input signal IN from the inverter IV
1
. The gate of the NMOS transistor TN
2
is supplied with the same phase signal of the input signal IN from the inverter IV
2
. That is, the gates of the NMOS transistors TN
1
and TN
2
are respectively supplied with complementary signals, which are complementary to each other.
The node Nb that is established between the drains of the PMOS transistor TP
2
and the NMOS transistor TN
2
is connected to the input terminal of the inverter IV
3
having a CMOS configuration, which operates based on the prescribed voltage of 5V. Therefore, the inverter IV
3
provides the output signal OUT, which is an inverse signal of a signal appearing at the node Nb.
The inverters IV
1
and IV
2
of the VDDL circuit system, and the level shift circuit LS and inverter IV
3
of the VDDH circuit system are all given the same ground potential of 0V, which is the reference potential in measurement of signal levels in the VDDL circuit system and VDDH circuit system. That is, the VDDL circuit system receiving the input signal IN has the prescribed signal level of 3V based on the reference ground potential, and the VDDH circuit system providing the output signal OUT has the prescribed signal level of 5V based on the reference ground potential.
Next, the overall operation of the signal level shift circuit of
FIG. 4A
will be described with reference to FIG.
4
B.
When the input signal IN is low (i.e., 0V) in the VDDL circuit system, the inverter IV
1
outputs a signal whose level is 3V, and the inverter IV
2
outputs a signal whose level is 0V. In the VDDH circuit system, the NMOS transistor TN
1
whose gate receives the output signal of the inverter IV
1
is turned on, while the NMOS transistor TN
2
whose gate receives the output signal of the inverter IV
2
is turned off.
Due to the ON state of the NMOS transistor TN
1
, the node Na is pulled down to a low level, so that the PMOS transistor TP
2
whose gate is connected with the node Na is turned on. At this time, the NMOS transistor TN
2
is turned off while the node Nb is pulled up to a high level (5V), so that the PMOS transistor TP
1
whose gate is connected with the node Nb is turned off. The inverter IV
3
receives the high level (5V) of the node Nb to provide the output signal OUT having a low level.
In contrast, when the input signal IN is high (i.e., 3V) in the VDDL circuit system, the inverter IV
1
outputs a signal whose level is 0V while the inverter IV
2
outputs a signal whose level is 3V. In this case, the NMOS transistor TN
1
is turned off while the NMOS transistor TN
2
is turned on. As a result, the node Nb is pulled down to the low level (0V), so that the IV
3
operating based on the low-level potential of the node Nb outputs a high-level signal OUT of 5V.
As described above, the signal level circuit of
FIG. 4A
works in such a way that the input signal whose level is 3V is converted to the output signal OUT whose level is 5V. Thus, it is possible to realize communication of signals between different circuit systems that operate based on different supply voltages respectively.
With respect to the PMOS transistor TP
1
and the NMOS transistor TN
1
that are connected in series between the power supply VDDH and the ground, the PMOS transistor TP
1
is turned off during the period in which the input signal IN is low (0V), while the NMOS transistor TN
1
is turned off during the period in which the input signal IN is high (3V). Therefore, there may be no possibility that a through current flows between the power supply VDDH and the ground via these transistors. Similarly, with respect to the PMOS transistor TP
2
and the NMOS transistor TN
2
that are connected in series between the power supply VDDH and the ground, one of these transistors is selectively turned off, which may indicate no possibility that a through current flows between the power supply VDDH and the ground via these transistors. That is, as long as the input signal IN is securely set to the high or low level, it is possible to reliably secure conversion of signal levels between different circuit systems without causing through currents to flow in the level shift circuit LS.
However, there still remains a problem in that through currents occur and flow in the level shift circuit LS supplied with the supply voltage VDDH when reduction occurs in the supply voltage VDDL.
Next, a description will be given with respect to the mechanism of occurrence of through currents in the level shift circuit LS. In the level shift circuit LS, as long as one of the NMOS transistors TN
1
and TN
2
is securely turned off, the PMOS transistors TP
1
and TP
2
are each complementarily turned on in association with the NMOS transistors TN
1
and TN
2
, so that no through current occur in the level shift circuit LS.
For some reason, however, when both the NMOS transistors TN
1
and TN
2
are temporarily turned on, both the nodes Na and Nb are simultaneously reduced in potentials, so that both the PMOS transistors TP
1
and TP
2
alternately connected with these nodes are simultaneously turned on. As a result, all the PMOS transistors TP
1
and TP
2
, and the NMOS transistors TN
1
and TN
2
are simultane
Maejima Toshio
Toda Akihiko
Pillsbury & Winthrop LLP
Wells Kenneth B.
Yamaha Corporation
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