Circuit for shaping digital signals in an integrated circuit

Details Circuit for shaping digital signals in an integrated circuit Circuit for shaping digital signals in an integrated circuit

1983-12-15

1986-06-24

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307360, 307517, 307555, 307550, 307263, H03K 508, H03K 512

Patent

active

045969361

ABSTRACT:
The present invention reduces rising and/or falling time delay of digital signals on poly-silicon layer wiring lines in semiconductors. Specific points of a network are fed with positive or negative voltage from a power source immediately after the initial rise and/or fall of the digital signals, and the potential at the specific point is rapidly pulled up or pulled down toward the source voltage. The pulling by the power source voltage is stopped when the potential reaches a specified value, and the pull-up or pull-down does not prevent subsequent operations. The signals reform or restore a square wave shape to the digital signals. The circuit includes a positive feedback circuit and a positive feedback cut-off circuit, each comprising an inverter and a transistor.

REFERENCES:
patent: 3631267 (1971-12-01), Heimbigner
patent: 3824408 (1974-07-01), Brunel
patent: 3989955 (1976-11-01), Suzuki
patent: 4217502 (1980-08-01), Suzuki et al.
patent: 4338678 (1982-06-01), Akatsuka
patent: 4449064 (1984-05-01), Eckert et al.
patent: 4491748 (1985-01-01), Chappell et al.
patent: 4494018 (1985-01-01), Clemen et al.
patent: 4498021 (1985-02-01), Uya
EP-A1-19241 (Nippon Electric Ltd.).

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