Circuit for setting a device into a test mode by changing a firs

Details Circuit for setting a device into a test mode by changing a firs Circuit for setting a device into a test mode by changing a firs

1996-07-01

1999-11-09

Pham, Chi H.

Pulse or digital communications

Testing

324527, 34082565, 364569, 364579, 371 221, H04B 346, H04B 1700, H04Q 122

Patent

active

059828153

ABSTRACT:
An apparatus for setting a device into a test mode. The apparatus has a first input port for receiving a fixed, constant signal during a normal mode of the device, and for receiving a non-fixed, clocked signal so as to set the device into a test mode. The apparatus also has a second input port for receiving a non-fixed, clocked signal during the normal mode and for receiving a fixed, constant signal so as to set the device into the test mode. When both the first input port receives the non-fixed, clocked signal and the second input port receives the fixed, constant signal for a predetermined amount of time, the device is placed into the test mode.

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Miyaji, et al. A Multibit Test Trigger Circuit for Megabit SRAM's, 8107 IEEE Journal of Solid-State Circuits 25 (Feb. 1990), No. 1, New York, US.
Chardon et al. Axe 10 Numerique: Raccordement D'Abonnes Analogiquies, 316 Commutation & Transmission 11 (1989) No. 4, Paris, FR, pp. 67-74.

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