Circuit for selectively providing maximum or minimum of a...

Details Circuit for selectively providing maximum or minimum of a... Circuit for selectively providing maximum or minimum of a...

2007-06-05

2007-06-05

Mai, Tan V. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S495000

Reexamination Certificate

active

10035746

ABSTRACT:
A floating point max/min circuit for determining the maximum or minimum of two floating point operands includes a first analysis circuit configured to determine a format of a first floating point operand of the two floating point operands based upon floating point status information encoded within the first floating point operand, a second analysis circuit configured to determine a format of a second floating point operand of the two floating point operands based upon floating point status information encoded within the second floating point operand, a decision circuit, coupled to the first analysis circuit and to the second analysis circuit and responding to a function control signal that indicates the threshold condition is one of a maximum of the two floating point operands and a minimum of the two floating point operands, for generating at least one assembly control signal based on the format of a first floating point operand, the format of a second floating point operand, and the function control signal, and a result assembler circuit, coupled to the decision circuit, for producing a result indicating which of the first floating point operand and the second floating point operand meet the threshold condition, based on the at least one assembly control signal. The format of the floating point operands may be from a group comprising: not-a-number (NaN), positive infinity, negative infinity, normalized, denormalized, positive overflow, negative overflow, positive underflow, negative underflow, inexact, exact, division by zero, invalid operation, positive zero, and negative zero. The result produced may be a third floating point operand having encoded floating point status information, and at least part of the encoded floating point status information in the result may come from either the first floating point operand or the second floating point operand.

REFERENCES:
patent: 3725649 (1973-04-01), Deerfield
patent: 4777613 (1988-10-01), Shahan et al.
patent: 4788655 (1988-11-01), Nakayama et al.
patent: 4991131 (1991-02-01), Yeh et al.
patent: 5065352 (1991-11-01), Nakano
patent: 5126963 (1992-06-01), Fukasawa
patent: 5161117 (1992-11-01), Waggener, Jr.
patent: 5249149 (1993-09-01), Cocanougher et al.
patent: 5307303 (1994-04-01), Briggs et al.
patent: 5347481 (1994-09-01), Williams
patent: 5347482 (1994-09-01), Williams
patent: 5357237 (1994-10-01), Bearden et al.
patent: 5363321 (1994-11-01), Dao Trong et al.
patent: 5365465 (1994-11-01), Larson
patent: 5481489 (1996-01-01), Yanagida et al.
patent: 5570310 (1996-10-01), Smith
patent: 5666301 (1997-09-01), Makino
patent: 5748516 (1998-05-01), Goddard et al.
patent: 5812439 (1998-09-01), Hansen
patent: 5862066 (1999-01-01), Rossin et al.
patent: 5892697 (1999-04-01), Brakefield
patent: 5931943 (1999-08-01), Orup
patent: 5953241 (1999-09-01), Hansen et al.
patent: 5963461 (1999-10-01), Gorshtein et al.
patent: 5978901 (1999-11-01), Luedtke et al.
patent: 5995991 (1999-11-01), Huang et al.
patent: 6009511 (1999-12-01), Lynch et al.
patent: 6049865 (2000-04-01), Smith
patent: 6081823 (2000-06-01), Purcell et al.
patent: 6105047 (2000-08-01), Sharangpani et al.
patent: 6108772 (2000-08-01), Sharangpani
patent: 6131106 (2000-10-01), Steele, Jr.
patent: 6138135 (2000-10-01), Karp
patent: 6151669 (2000-11-01), Huck et al.
patent: 6189094 (2001-02-01), Hinds et al.
patent: 6205460 (2001-03-01), Steele, Jr.
patent: 6219685 (2001-04-01), Story
patent: 6256655 (2001-07-01), Ezer et al.
patent: 6286023 (2001-09-01), Purcell et al.
patent: 6286024 (2001-09-01), Yano et al.
patent: 6360189 (2002-03-01), Hinds et al.
patent: 6393555 (2002-05-01), Meier et al.
patent: 6490607 (2002-12-01), Oberman
patent: 6571265 (2003-05-01), Story
patent: 6594681 (2003-07-01), Prabhu
patent: 6629120 (2003-09-01), Walster et al.
patent: 6658443 (2003-12-01), Walster
patent: 6658444 (2003-12-01), Walster et al.
patent: 6697832 (2004-02-01), Kelley et al.
patent: 6732134 (2004-05-01), Rosenberg et al.
patent: 6789098 (2004-09-01), Dijkstra
patent: 2002/0194232 (2002-12-01), Walster
patent: 2003/0033335 (2003-02-01), Walster
U.S. Appl. No. 10/320,547, filed Dec. 17, 2002, Steele, Jr.
U.S. Appl. No. 10/320,450, filed Dec. 17, 2002, Steele, Jr.
U.S. Appl. No. 10/028,375, filed Dec. 28, 2001, Steele, Jr.
U.S. Appl. No. 10/035,579, filed Dec. 28, 2001, Steele, Jr.
U.S. Appl. No. 10/035,580, filed Dec. 28, 2001, Steele, Jr.
U.S. Appl. No. 10/035,581, filed Dec. 28, 2001, Steele, Jr.
U.S. Appl. No. 10/035,582, filed Dec. 28, 2001, Steele, Jr.
U.S. Appl. No. 10/035,583, filed Dec. 28, 2001, Steele, Jr.
U.S. Appl. No. 10/035,584, filed Dec. 28, 2001, Steele, Jr.
U.S. Appl. No. 10/035,585, filed Dec. 28, 2001, Steele, Jr.
U.S. Appl. No. 10/035,586, filed Dec. 28, 2001, Steele, Jr.
U.S. Appl. No. 10/035,587, filed Dec. 28, 2001, Steele, Jr.
U.S. Appl. No. 10/035,589, filed Dec. 28, 2001, Steele, Jr.
U.S. Appl. No. 10/035,595, filed Dec. 28, 2001, Steele, Jr.
U.S. Appl. No. 10/035,647, filed Dec. 28, 2001, Steele, Jr.
U.S. Appl. No. 10/035,674, filed Dec. 28, 2001, Steele, Jr.
U.S. Appl. No. 10/035,741, filed Dec. 28, 2001, Steele, Jr.
U.S. Appl. No. 10/035,747, filed Dec. 28, 2001, Steele, Jr.
U.S. Appl. No. 10/036,133, filed Dec. 28, 2001, Steele, Jr.
Title: “Safe Treatment of Overflow and Underflow Conditions”, by Robert A. Fraley & J. Stephen Walther, Hewlett-Packard Co., pp. 1-5.
Title: “Vax Floating Point: A Solid Foundation for Numerical Computation”, by Mary Payne & Dileep Bhandarkar, Digital Equipment Corp., pp. 1-12.
Title: Lecture Notes on the Status of “IEEE Standard 754 for Binary Floating-Point Arithmetic”, by Prof. W. Kahan, May 31, 1996, pp. 1-30.
Title: “Interval Arithmetic Specification” by Dmitri Chiriaev & G. William Walster, Draft revised May 4, 1998, pp. 1-78.
Title: “IEEE Standard for Binary Floating-Point Arithmetic IEEE Standard 754-1985,” by Standards Committee of the IEEE Computer Society, The Institute of Electrical and Electronics Engineers, Inc., copyright 1985, pp. 1-14.

Affiliated with

Also associated with

Rating

Circuit for selectively providing maximum or minimum of a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit for selectively providing maximum or minimum of a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for selectively providing maximum or minimum of a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3859532