Static information storage and retrieval – Magnetic bubbles – Guide structure
Patent
1995-03-03
1997-04-29
Ray, Gopal C.
Static information storage and retrieval
Magnetic bubbles
Guide structure
395729, 395293, 395299, 395433, 365222, G06F 1316, G06F 1336
Patent
active
056258240
ABSTRACT:
An improved arbitration scheme including multiple arbiters for arbitrating access to a PCI bus and an ISA bus. The PCI arbiter controls access to the PCI bus by various bus masters, including the CPU/main memory subsystem, various other PCI bus masters, an enhanced DMA or EDMA controller, and an 8237-compatible DMA controller. The PCI arbiter utilizes a modified LRU arbitration scheme. Further, an SD arbiter exists to arbitrate access to the data portion (SD) of the ISA bus. The various devices that may request the SD bus include the EDMA controller, a PCI master in a PCI-to-ISA operation, the DMA controller, an ISA bus master, and the refresh controller. The SD arbiter assigns the highest priority to the PCI bus, followed by the refresh controller, EDMA controller, and DMA controller or ISA bus masters. The DMA controller includes an arbiter for arbitrating between its channels. The DMA arbiter further includes logic to ensure that the DMA controller or ISA bus master relinquishes control of the ISA bus after one arbitration cycle.
REFERENCES:
patent: 4473880 (1984-09-01), Budde et al.
patent: 4602327 (1986-07-01), Laviolette et al.
patent: 4663756 (1987-05-01), Retterath
patent: 4755938 (1988-07-01), Takahashi et al.
patent: 4760515 (1988-07-01), Malmquist et al.
patent: 4785394 (1988-11-01), Fischer
patent: 4980854 (1990-12-01), Donaldson et al.
patent: 4987529 (1991-01-01), Craft et al.
patent: 5127089 (1992-06-01), Gay et al.
patent: 5239631 (1993-08-01), Boury et al.
patent: 5265223 (1993-11-01), Brockmann et al.
patent: 5418920 (1995-05-01), Kuddes
82420/82430 PCI SET, ISA and EISA Bridges, Intel Corp., pp. 3-5, 17, 35, 37, 148, 154-157, 172-174, 211, 225-226, 293-302, 320-321, 345, 363-364, 438-444, 460-462 (1993).
IBM Technical Disclosure Bulletin, vol. 34, No. 2, Jul. 1991, "Shared Memory Design with Input and Output Queues", pp. 400-403.
Patent Abstracts of Japan, vol. 16, No. 520 (P-1444), Oct. 26, 1992 & JP-A-04 192056 (Fujitsu Ltd.) Jul. 10, 1992, Abstract Only.
Bonella Randy M.
Melo Maria L.
Tucker Brian B.
Compaq Computer Corporation
Ray Gopal C.
LandOfFree
Circuit for selectively preventing a microprocessor from posting does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit for selectively preventing a microprocessor from posting, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for selectively preventing a microprocessor from posting will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-714702