Patent
1995-11-14
1999-10-19
Trans, Vincent N.
G06F 1338
Patent
active
059702362
ABSTRACT:
A circuit for selectively performing big-endian/little-endian data format conversion based on whether instructions or data are being transferred. The data and instructions are allocated to different regions in memory so that the big-endian/little-endian conversion is based on the source or destination address of the requested operation. Registers are provided to define a lower bound address and an upper bound address. In addition, a separate register is provided which indicates whether the data is stored between the lower bound and upper bound addresses or outside the lower bound and upper bound addresses. The registers are write addressable through the PCI configuration space, the memory space, and the I/O space, which allows the values in the registers to be changed dynamically during computer system operation.
REFERENCES:
patent: 5201039 (1993-04-01), Sakamura
patent: 5410677 (1995-04-01), Roskowski et al.
patent: 5446482 (1995-08-01), Van Aken et al.
patent: 5550987 (1996-08-01), Tanaka
patent: 5574923 (1996-11-01), Heeb et al.
patent: 5604885 (1997-02-01), Denio
Intel.RTM. Pentium.RTM. Processor User's Manual vol. 3: Architecture and Programming Manual, pp. 25-32, 1993.
Fibre Channel Physical and Signalling Interface Specificaiton, Rev. 4.3 (Jun. 1994).
Callison Ryan A.
Galloway William C.
Compaq Computer Corporation
Trans Vincent N.
LandOfFree
Circuit for selectively performing data format conversion does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit for selectively performing data format conversion, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for selectively performing data format conversion will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2067184