Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Converging with plural inputs and single output
Reexamination Certificate
2000-04-25
2003-02-25
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Converging with plural inputs and single output
C327S099000, C327S200000
Reexamination Certificate
active
06525591
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a circuit for selectively enabling one circuit from among a plurality of circuit alternatives of an integrated circuit.
BACKGROUND OF THE INVENTION
When designing integrated circuits, it is often necessary to choose from among several circuit alternatives, frequently each circuit alternative having quite different characteristics.
Choosing one circuit solution over the others possible involves the exclusion of the other circuit alternatives. However, it may happen that the solution chosen during the design phase is not practically the best one. Additionally, after one circuit solution has been chosen, switching to another alternative solution initially discarded involves remaking all or at least some of the photolithographic masks used in the manufacturing process. This obviously causes an increase in the manufacturing costs. Moreover, whenever one or more photolithographic masks have to be redesigned, there is always the possibility of incurring in new errors. This causes an increase in the testing phase.
Therefore, in practice the designer of an integrated circuit provides, whenever it is possible, for the implementation of more than one circuit alternative for at least some of the circuit blocks. The provision of such circuit alternatives, or “options,” involves providing alternative metal interconnection lines that can be disabled during the testing of the device. For example, assuming that it is desired to provide more than one possibility for the control signal of a generic circuit block, it is possible to provide a multiplexer supplied with several signals, among which the one most suitable for driving the circuit block is to be determined. During the testing of the device, it is possible to deliberately interrupt some of the electrical interconnection lines in such a way that the multiplexer output switches among all the possible driving signals. Once the best circuit alternative has been determined, the photolithographic mask defining the metal interconnections, which is typically one of the last masks in the manufacturing process flow, will be redesigned so as to render the chosen alternative definitive.
However, configuring the multiplexer, or more generally configuring the combinatorial circuits that allow experimentation of more than one option, by interrupting the metal interconnection lines has the disadvantage of leaving the inputs of the logic circuits connected to the interrupted interconnection lines floating, and not at a well-defined logic level. This causes indetermination of the integrated circuit performance and increases the device's power consumption because of the absence of well-defined logic levels.
In order to configure the combinatorial circuits that choose from among the several circuit alternatives possible, it is also possible to use programmable non-volatile memory elements. However, this approach normally complicates the manufacturing process because the process technology for the integration of the memory elements must be used.
Similarly, other testing solutions may be implemented. For example, using so-called “third-levels” of voltage applied to the input terminals of the integrated circuit. However, these solutions require the use of specially-designed circuits, which result in an increase in the design costs and in the device area.
SUMMARY OF THE INVENTION
According to the principles of the present invention, a circuit is provided for selectively enabling one circuit from among a plurality of circuit alternatives of an integrated circuit. The circuit provided does not involve overly complex circuit networks and does not require specific technological processes for its integration. The circuit allows for simple experimental testing of a plurality of alternative circuit solutions while overcoming the previously mentioned problems related to the absence of well-defined logic levels inside the integrated circuit, which may introduce anomalous current paths. It also does not require a complex redesign to implement the best circuit alternative once it has been determined.
According to the present invention, such object is attained by means of a circuit for selectively enabling one among a plurality of circuit alternatives of an integrated circuit, comprising selection circuit means for selecting one circuit from among the circuit alternatives. The selection means are controlled by a bistable circuit means having a preferred state. Disactivatable forcing means associated to the bistable means are provided for forcing the bistable means into a state opposite to the preferred state, so that when the forcing means are disactivated, the bistable circuit means automatically switches to the preferred state.
Thanks to the present invention, it is possible to test several alternative circuit solutions by simply integrating in the integrated circuit a small and simple network that can be realized in any technological process. The circuit of the present invention, comprising bistable means, does not introduce current consumption, particularly with regards to any current consumption caused by the uncertainty of the logic level of signals driving the logic gates. The circuit of the invention also does not require any complicated test procedures which are normally involved with the use of complex circuit networks.
These and other features and advantages of the present invention will be made apparent by the following detailed description of two particular embodiments thereof, illustrated as non-limiting examples in the annexed drawings.
REFERENCES:
patent: 4614881 (1986-09-01), Yoshida et al.
patent: 5557221 (1996-09-01), Taguchi et al.
patent: 5706232 (1998-01-01), McClure et al.
patent: 6100740 (2000-08-01), Pascucci
patent: 6297992 (2001-10-01), Oh
IBM Technical Disclosure Bulletin, vol. 30, No. 12, May 1988.*
IBM Technical Disclosure Bulletin, vol. 30, No. 2, May 1988.
Jorgenson Lisa K.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
Tarleton E. Russell
Wells Kenneth B.
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