Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
1998-11-20
2001-01-23
Jean Pierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S155000
Reexamination Certificate
active
06177900
ABSTRACT:
FILED OF THE INVENTION
The present invention relates to a circuit for selecting one of divided encoders for an analog to digital (A/D) converter, and more particularly to an A/D converter in which high speed A/D conversion operation is realized and power consumption is decreased.
BACKGROUND OF THE INVENTION
As a conventional A/D converter, for example, Japanese Patent Application Laid-Open No. 9-8662 discloses an encoding circuit for an A/D converter having a bit line divisional buffer, in which bit lines of encoders are divided into plurality such that the number of transistors connected to bit lines is reduced, so as to reduce a precharging time and an encoding time of the encoders.
FIG. 1
shows a conventional encoding circuit, wherein the encoding circuit comprises selection transistors
117
which serves as selection transistor switches for discharging bit lines, code selection signal terminals
118
for controlling the selection transistors
117
by code selection signal, and bit lines
119
to
121
, to each of which selection transistors
117
are connected.
The encoding circuit further comprises bit line precharging transistors
115
, encoding transistors
116
, and a control signal terminal
114
for controlling the precharging transistors
115
by control signals, and the encoding transistors
116
discharge the bit lines
119
to
121
, when the selection transistors
117
are turned on. First and second encoders
133
and
134
are composed of the selection transistors
117
, the bit lines
119
to
121
, the precharging transistors
115
and the encoding transistors
116
, respectively.
Encoded signals
135
output from the first encoder
133
are input to first input terminals of a bit line divisional buffer
137
comprising AND circuits
138
, and encoded signals
136
output from the second encoder
134
are input to second input terminals of the bit line divisional buffer
137
.
In the conventional encoding circuit, a charge loaded on the bit line is decreased by dividing the bit lines into plural encoders, and the logic signals divided into plural groups are synthesized by a single bit line divisional buffer provided at the next stage.
Next, operation of the conventional encoding circuit will be explained.
First, when the control signal input to the control signal terminal
114
becomes to L (low) level, in the first and second encoders
133
and
134
, the respective precharging transistors
115
thereof are switched to ON state and the respective encoding transistors
116
thereof are switched to OFF state.
Next, all of the bit lines
119
to
121
of the first and second encoders
133
and
134
are precharged via the precharging transistors
115
by a power source.
During the period when the control signal of the control signal terminal
114
is kept at the L level, data to be converted are transmitted to the code selection signal terminal
118
(P
0
to P
7
), and it is determined whether the respective selection transistors
117
should be switched to ON or OFF state in response thereto. Among the code selection signal terminal P
0
to P
7
, the code selection signal terminal P
5
is connected to an encoder (not shown), which encodes all of the 3-bits to be “1”.
Then, all of the bit lines
119
to
121
in the first and second encoders
133
and
134
are sufficiently charged, and the states of the respective selection transistors
117
are determined such that the data should be converted into a desired binary code. Thereafter, the control signal input to the control signal terminal
114
becomes to H (high) level, and the selection transistors
117
are switched to ON or OFF state in response to a signal “1” or “0” which is input to the code selection signal terminals P
0
to P
7
, then some of the bit lines are discharged by the selection transistors
117
of the ON state and the encoding transistor
116
which is turned on.
Encoded signals
135
(D
10
to D
12
) and
136
(D
20
to D
22
) are output from the first and second encoders, respectively. Finally, the encoded signals
135
and
136
are input to the bit line divisional buffer
136
, and signals synthesized thereat are output as a desired binary code signal from digital signal output terminals
122
(G
0
to G
2
).
However, according to the conventional bit line divisional encoding circuit, there are following disadvantages.
The first disadvantage is that when data to be converted are provided in a certain order, some of bit lines are unnecessarily precharged, so that the electric power is excessively consumed.
The second disadvantage is that since divided data should be synthesized, time delay is occurred at a logic signal-sythesizing circuit.
The third disadvantage is that an operation state requires two steps of precharging period and active (discharging) period. Accordingly, for the purpose of conducting a converting operation with a higher speed, time duration of the active period in which the data is fixed can not help being excessively reduced, or a converting operation speed for the whole A/D converting circuit is determined by the structure of the encoding circuit.
The fourth disadvantage is that, since the bit lines may be at floating state in some case during the active period, it becomes difficult to apply the encoding circuit to operation requiring only the low-speed conversion, thereby reducing freedom of circuit design.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention is to provide a circuit for selecting one of divided encoders for an A/D converter, in which the operating speed is improved, and at the same time, unnecessary power consumption is prevented.
It is another object of the invention to provide a circuit for selecting one of divided encoders for an A/D converter for which freedom of circuit design is high.
According to the invention, a circuit for selecting one of divided encoders for an A/D converter, comprises:
means for generating a thermometric code of plural bits having a level determined by a level of an analog signal to be converted to a digital signals;
first to Nth encoders for encoding the thermometric code to provide the digital signal, each of the first to Nth encoders being supplied with a corresponding group of bits obtained by dividing the plural bits of the thermometric code by N, where N is an integer equal to or more than 2; and
means for selecting one of the first to Nth encoders in accordance with a high or low level state(s) of a bit(s) at an (N−1)-dividing position(s) in division of the plural bits of the thermometric code by N, the one of the first to Nth encoders providing the digital signal converted from the analog signal.
According to the invention, since a logic signal-synthesizing circuit after dividing data lines is no longer necessary, a high speed operation with lower power consumption can be realized.
Further, according to the invention, since encoders are generally operated exclusively or independently from the other circuits, by supplying parts of a thermometric code as control signals output from comparators at a previous stage to divided encoders, the encoding bit lines are not precharged unnecessarily and the power consumption can be reduced.
Still further, according to the invention, since the thermometric code is directly provided as control signals for divided encoders, an encoder-dividing control circuit can be simplified.
The divided encoders and data line-dividing circuit are provided, so that it is not necessary to provide a complicated timing design, which has been required for the conventional high-speed A/D converter, and it is possible to apply a static type logic circuit to a low-speed A/D converter device. Namely, the freedom of circuit design can be improved.
REFERENCES:
patent: 5155489 (1992-10-01), Gulczynski
patent: 5243348 (1993-09-01), Jackson
patent: 5252974 (1993-10-01), Gulczynski
patent: 5877720 (1999-03-01), Setty et al.
patent: 5955980 (1999-09-01), Hanna
patent: 5-75643 (1993-03-01), None
patent: 9-8662 (1997-01-01), None
Jean Pierre Peguy
NEC Corporation
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