Pulse or digital communications – Receivers – Angle modulation
Reexamination Certificate
1998-12-15
2002-04-23
Chin, Stephen (Department: 2634)
Pulse or digital communications
Receivers
Angle modulation
C375S355000
Reexamination Certificate
active
06377634
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a circuit for reproducing bit timing, and more particularly to such a circuit for detecting a timing gap between a sampling clock and an optimal sampling clock, based on a real part digital signal and an imaginary part digital signal obtained by digitizing a real part and an imaginary part of a complex modulation signal having a base band frequency band and obtained from a received modulation signal modulated into a digital phase.
2. Description of the Related Art
An apparatus for demodulating burst signals having been modulated into a digital phase is often provided at an input stage thereof with an automatic gain control circuit (hereinafter, referred to simply as “AGC”) in order to suppress fluctuation in received signals in a transmission path. It is necessary to use a preamble in order to converge AGC.
As is well known, a preamble is a signal indicating that data to be transmitted from a transmitter to a receiver at any time has been transmitted to a receiver, and establishing synchronization between a transmitter and a receiver.
A burst signal having been modulated into a digital phase is designed to have a preamble at the head thereof for reproducing bit timing, to thereby establish synchronization.
Bit timing of quadrature phase shift keying (QPSK) is usually reproduced through the use of a preamble pattern in which signals existing on a diagonal line are repeatedly transmitted in such an arrangement of signal points as an arrangement illustrated in
FIG. 3
, which is a signal phase diagram, and has I-axis as an axis of abscissa and Q-axis as an axis of ordinate.
The above-mentioned reproduction of bit timing is controlled, for instance, by zero-cross detection in which timing at which a signal passes an origin is detected.
In zero-cross detection, there is used sampling data having a small amplitude around an origin. However, sampling data having a small amplitude is accompanied with a problem of being readily influenced by noises and non-linear strains to thereby generate errors.
In burst transmission system making use of digital phase modulation, it is necessary to rapidly carry out bit synchronization and demodulation such as reproduction of a carrier wave. To this end, a burst signal is provided at a head thereof with a preamble.
In order to enhance a transmission rate, it is preferable to shorten a preamble to thereby rapidly establish bit synchronization.
For instance, Japanese Unexamined Patent Publication No. 5-211532 has suggested a rapid bit synchronization system in which a &pgr;/2-shifted BPSK signal or a &pgr;/4-shifted QPSK signal is employed, and needs to have a zero-&pgr;/2 modulated preamble or a zero-3&pgr;/4 modulated preamble, respectively.
A signal obtained by detecting a &pgr;/2-shifted BPSK signal or a &pgr;/4-shifted QPSK signal in quasi-synchronization is digitally quantized into one bit signal by means of an analog-digital converter through the use of clock signals transmitted from an oscillator, and then, variation in phase is detected by a phase-variation detector.
A complex sine wave generator generates a complex sine wave having a frequency of N/2 in response to a clock signal transmitted from an oscillator. A multiplier multiplies the thus generated complex sine wave by the variation in phase detected by the phase-variation detector to thereby calculate a relation in phase between a frequency component of 1/2 bit and the complex sine wave. The result of calculation is averaged through a low-pass filter, and then, a reverse tangent of an output transmitted from the low-pass filter is calculated by a reverse tangent calculator.
The reverse tangent calculator transmits its output at a timing which is represented within ±&pgr; under a two-bit interval. In order to covert a bit timing of an output timing of the reverse tangent calculator into a bit timing represented within ±&pgr; under a one-bit interval, the reverse tangent is doubled by means of a doubling device, and a remainder is calculated when the thus doubled reverse tangent is divided by 2&pgr;.
An output transmitted from an analog-digital converter is sampled or interpolated by a sampler or an interpolator at a bit timing at which the doubling device generates an output.
Japanese Unexamined Patent Publication No. 5-260107 has suggested a perpendicular modulator for demodulating n-PSK wave signals, wherein n indicates phase modulation. The suggested perpendicular modulator interpolates sampled n-PSK wave signals when n-PSK wave signals are digitally sampled and perpendicularly detected.
The suggested perpendicular modulator is designed to include two analog-digital converters for sampling n-PSK wave signals at a constant interval to thereby reproduce base band signals. Then, the thus reproduced base band signals are interpolated by means of an interpolation circuit. A re-timing device carries out re-timing treatment to the thus interpolated base band signals in response to a bit timing signal. Then, a detector detects the thus re-timed base band signals to thereby reproduce data sequence. Then, a bit timing reproducer generates a bit timing signal, based on a timing of the thus reproduced data sequence.
Japanese Unexamined Patent Publication No. 6-284159 has suggested a digital demodulator including a clock synchronization circuit which extracts a phase component of received clocks, and control a phase of a timing clock.
In accordance with the suggested digital demodulator, a base band signal having been modulated under four-value digital modulation is sampled at a rate twice greater than a modulation rate to thereby convert the base band signal into digital data. Detection data detected by a delay detection circuit is judged by a judgement circuit with judgement timing clocks, and then, is transmitted to a limiter circuit having a function of interpolation.
The limiter circuit interpolates one or more of adjacent two sampling values of detected outputs, puts the thus interpolated value into a limiter, and transmits one-bit interpolated data to a digital band pass filter.
In response to transmission of an output from the digital band pass filter, a circuit for detecting an error in phase detects an error in phase in a timing clock. Then, the circuit for detecting an error in phase transmits a signal indicative of an error in phase to a circuit for reproducing a clock, in accordance with the result of comparison in phase between the thus detected error in phase and a current timing clock. Then, the circuit for reproducing a clock compensates for a phase of a timing clock.
Japanese Unexamined Patent Publication No. 7-50700 has suggested a circuit for reproducing a carrier wave for detecting a phase of preamble.
In the suggested circuit, first and second multipliers each multiplies an offset QPSK modulation wave by a reproduced carrier wave having a phase shifted by &pgr;/2 from a phase of the offset QPSK modulation wave. An output transmitted from the first multiplier is delayed by a half interval of symbol rate relative to an output transmitted from the second multiplier, by means of a delay circuit. Then, a phase comparator for reproducing a bit timing converts outputs transmitted from the delay circuit and the second multiplier into a signal having a phase including two phase-stable points.
Japanese Unexamined Patent Publication No. 7-212419 has suggested an apparatus for extracting a clock for detecting a phase of preamble.
In this apparatus, a relative phase of a carrier wave of a &pgr;/4-shifted QPSK is input into a relative phase detector. The relative phase detector includes first and second counters each of which counts signals having a frequency equal to a M times multiplied sum of a frequency of a carrier wave of a &pgr;/4-shifted QPSK signal transmitted from an oscillator and a shifted frequency.
The relative phase detector includes an amplitude limiter. The amplitude limiter slides an amplitude of the carrier wave to thereby transmit a rectangular wave as a carrier wave. A rise-u
Fan Chieh M.
NEC Corporation
Whitman, Curtis & Christofferson P.C.
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