Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data
Reexamination Certificate
1998-05-22
2001-02-20
Bocure, Tesfaldet (Department: 2731)
Pulse or digital communications
Synchronizers
Synchronizing the sampling time of digital data
C375S340000
Reexamination Certificate
active
06192091
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital multilevel QAM (quadrature amplitude modulation) demodulation, and more specifically to a clock reproducing circuit for reproducing a clock from a multilevel QAM signal.
2. Description of Related Art
A multilevel QAM transmission system, which is one of digital transmission systems, now attracts attention in the field requiring the transmission of a large amount of digital data, such as a bi-directional TV, an internet distribution using a cable modem, etc.
One of major technologies in the multilevel QAM demodulation, is a clock reproduction, which is a technology for reproducing a clock in synchronism with a data rate, on the basis of a multilevel QAM signal supplied from a multilevel QAM modulator. The clock reproduction is a key for realizing a stable demodulation.
Referring to
FIG. 1
, there is shown a block diagram illustrating a construction of a conventional multilevel QAM demodulation system. In
FIG. 1
, Reference Numeral
522
designates an input terminal, and Reference Numerals
523
and
524
indicate a multiplication-detection circuit (mixer). Reference Numeral
525
shows a carrier reproducing circuit, and Reference Numeral
526
denotes a 90° phase shifter. Reference Numerals
527
and
529
designate a low pass filter, and Reference Numerals
528
and
530
indicate an analog to digital (A/D) converter. Reference Numeral
531
shows a QAM demodulation circuit, and Reference Numeral
532
denotes an output terminal. Reference Numeral
533
designates a clock reproducing circuit, and Reference Numeral
534
indicates clock phase error detection circuit. Reference Numeral
535
shows a loop filter, and Reference Numeral
536
denotes a voltage controlled oscillator (VCO). “I” designates an analog in-phase signal, and “Q” shows an analog quadrature signal. “I
D
” shows a digital in-phase signal, and “Q
D
” denotes a digital quadrature signal.
A multilevel QAM signal supplied through the input terminal
522
shown in
FIG. 1
is branched into two paths, which are connected to the multiplication-detection circuits
523
and
524
, respectively. In addition, an output of the carrier reproducing circuit
525
is also branched into two paths, and one of which is supplied to one of the multiplication-detection circuits
523
, and the other of which is phase-shifted by the 90° phase shifter
526
and supplied to the other multiplication-detection circuit
524
. Thus, the multiplication-detection circuits
523
and
524
carry out the multiplication-detection to output a demodulated analog in-phase signal “I” and a demodulated analog quadrature signal “Q” through the low pass filters
527
and
529
to the A/D converters
528
and
530
, respectively, which generate a coded digital in-phase signal “I
D
” and a coded digital quadrature signal “Q
D
”.
Either of the coded signals “I
D
” and “Q
D
” (the signal “I
D
” in the shown example) is supplied to the clock reproducing circuit
533
, in which the coded signal is inputted to the clock phase error detecting circuit
534
, which then outputs a phase error signal through the loop filter
535
to supply a control voltage to the voltage controlled oscillator
536
. This voltage controlled oscillator
536
generates a clock to be supplied to the A/D converters
528
and
530
and the QAM demodulation circuit
531
. Thus, the clock is reproduced.
In order to reproduce the clock in the multilevel QAM demodulation circuit, Japanese Patent Application Pre-examination Publication No. JP-A-06-276247 (the content of which is incorporated by reference in its entirety into this application, and also an English abstract of JP-A-06-276247 is available from the Japanese Patent Office and the content of the English abstract of JP-A-06-276247 is also incorporated by reference in its entirety into this application) proposed an approach of utilizing, as a phase error signal, a signal delayed from a present input signal by a half of data period (½-data-period delayed signal) when the present input signal and a one-data-period delayed signal are in a certain relation.
Referring to
FIG. 2
, there is a graph illustrating a signal change in a prior art clock phase error detecting circuit. In this graph, Reference Numeral
601
designates a level discriminating range. In the clock phase error detecting circuit proposed by the above referred Japanese patent publication, attention is focused to the signal which changes as signals “a” and “b” shown in
FIG. 2
, during one data period, for the purpose of detecting a phase error. Namely, the signal so changes that the chain line in
FIG. 2
, which approximates the change between the signals “a” and “b” to a straight line, crosses the straight line “0” at a level “0”. In the following, the signal change that the chain line crosses the straight line “0”, will be called a “zero cross change”, and the intersection between the chain line and the straight line “0” will be called a “zero cross point”. In addition, an intermediate point of one data period will be called a ½-data-period-point”.
Under this assumption, paying attention to the data at the ½-data-period-point, if the clock and the data are in synchronism, it becomes ½-data-period-point=zero cross point, so that an average of the signal becomes zero. However, if the clock and the data are out of synchronism, the average of the signal has some value, which can be considered to be the phase error.
Referring to
FIG. 3
, there is shown a block diagram illustrating the construction of the prior art clock phase error detecting circuit. In
FIG. 3
, Reference Numeral
701
designates an input terminal, and Reference Numerals
702
and
703
show a delay circuit. Reference Numeral
704
indicates a subtraction circuit, and Reference Numerals
705
and
711
denote a discrimination circuit. Reference Numerals
706
and
712
designate a threshold value input terminal, and Reference Numeral
707
shows a sign inversion circuit. Reference Numeral
708
indicates a gate circuit, and Reference Numeral
709
denotes an output terminal. Reference Numeral
710
designates an addition circuit. Reference Character “a” shows an input signal, and Reference Character “b” indicates a one-data-period delay signal. Reference Character “c” denotes a ½-data-period delayed signal, and Reference Character “f” designates a phase error signal.
In this prior art clock phase error detecting circuit, the input signal “a” supplied through the input terminal
701
is supplied directly to one input of the subtraction circuit
704
, and also supplied through the two delay circuits
702
and
703
, as the one-data-period delay signal “b”, to the other input of the subtraction circuit
704
, which outputs a subtraction result (a−b). At the same time, the input signal “a” and the one-data-period delay signal “b” are supplied to the addition circuit
710
, which outputs an addition result (a+b). On the basis of the subtraction result (a−b), the sing inversion circuit
707
inverts or does not invert the ½-data-period delayed signal “c” outputted from the delay circuit
702
, so that the phase error signal “f” is outputted from the sing inversion circuit
707
. The discrimination circuit
705
discriminates which of the absolute value |a−b| of the subtraction result of the subtraction circuit
704
and a threshold supplied from the input terminal
706
is large. The discrimination circuit
711
discriminates which of the absolute value |a+b| of the addition result of the addition circuit
710
and a threshold supplied from the input terminal
712
is large. On the basis of respective discrimination results of the two discrimination circuits
705
and
711
, the gate circuit
708
is controlled either to output the phase error signal “f” outputted from the sing inversion circuit
707
to the output terminal
709
, or to maintain a preceding output.
Here, in the discrimination circuit
705
,
Bocure Tesfaldet
McGuireWoods LLP
NEC Corporation
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